Lines Matching refs:serverworks_private
45 } serverworks_private;
78 tables = serverworks_private.gatt_pages;
79 for (i = 0; i < serverworks_private.num_tables; i++) {
113 serverworks_private.num_tables = nr_tables;
114 serverworks_private.gatt_pages = tables;
121 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
150 retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
157 writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
158 writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
164 serverworks_free_page_map(&serverworks_private.scratch_dir);
177 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
182 writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
196 serverworks_free_page_map(&serverworks_private.scratch_dir);
208 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
209 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
211 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
212 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
239 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
241 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
244 dev_err(&serverworks_private.svrwrks_dev->dev,
250 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
252 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
255 dev_err(&serverworks_private.svrwrks_dev->dev,
272 pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
274 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
275 if (!serverworks_private.registers) {
280 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
281 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
283 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
284 readl(serverworks_private.registers+SVWRKS_GATTBASE); /* PCI Posting. */
286 cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
289 writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
290 readw(serverworks_private.registers+SVWRKS_COMMAND);
292 pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
294 pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
297 agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
300 pci_read_config_dword(serverworks_private.svrwrks_dev,
316 iounmap((void __iomem *) serverworks_private.registers);
404 pci_read_config_dword(serverworks_private.svrwrks_dev,
415 pci_write_config_dword(serverworks_private.svrwrks_dev,
483 serverworks_private.svrwrks_dev = bridge_dev;
484 serverworks_private.gart_addr_ofs = 0x10;
494 serverworks_private.mm_addr_ofs = 0x18;
496 serverworks_private.mm_addr_ofs = 0x14;
498 pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
501 serverworks_private.mm_addr_ofs + 4, &temp2);
514 bridge->dev_private_data = &serverworks_private,
528 pci_dev_put(serverworks_private.svrwrks_dev);
529 serverworks_private.svrwrks_dev = NULL;