Lines Matching defs:intel_private
91 } intel_private;
96 *ret = pci_map_page(intel_private.pcidev, page, 0,
98 if (pci_dma_mapping_error(intel_private.pcidev, *ret))
105 pci_unmap_page(intel_private.pcidev, dma,
138 mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
154 pci_unmap_sg(intel_private.pcidev, mem->sg_list,
173 intel_private.gtt+j);
187 intel_private.gtt+j);
192 readl(intel_private.gtt+j-1);
205 intel_private.gtt+j);
208 readl(intel_private.gtt+j-1);
246 if (!intel_private.registers) {
247 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
250 intel_private.registers = ioremap(temp, 128 * 4096);
251 if (!intel_private.registers) {
252 dev_err(&intel_private.pcidev->dev,
258 if ((readl(intel_private.registers+I810_DRAM_CTL)
261 dev_info(&intel_private.pcidev->dev,
263 intel_private.num_dcache_entries = 1024;
265 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
267 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
268 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
272 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
274 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
282 writel(0, intel_private.registers+I810_PGETBL_CTL);
283 readl(intel_private.registers); /* PCI Posting. */
284 iounmap(intel_private.registers);
386 intel_private.registers+I810_PTE_BASE+(i*4));
388 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
397 intel_private.registers+I810_PTE_BASE+(j*4));
399 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
421 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
423 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
475 if (pg_count != intel_private.num_dcache_entries)
539 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
565 dev_info(&intel_private.pcidev->dev,
596 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
610 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
748 intel_private.gtt_entries = gtt_entries;
753 kunmap(intel_private.i8xx_page);
754 intel_private.i8xx_flush_page = NULL;
755 unmap_page_from_agp(intel_private.i8xx_page);
757 __free_page(intel_private.i8xx_page);
758 intel_private.i8xx_page = NULL;
764 if (intel_private.i8xx_page)
767 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
768 if (!intel_private.i8xx_page)
771 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
772 if (!intel_private.i8xx_flush_page)
788 unsigned int *pg = intel_private.i8xx_flush_page;
813 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
816 intel_private.registers = ioremap(temp, 128 * 4096);
817 if (!intel_private.registers)
820 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
825 if (intel_private.gtt_entries == 0) {
826 iounmap(intel_private.registers);
884 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
891 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
892 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
895 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
896 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
898 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
909 iounmap(intel_private.registers);
926 if (pg_start < intel_private.gtt_entries) {
927 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
928 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
929 pg_start, intel_private.gtt_entries);
931 dev_info(&intel_private.pcidev->dev,
958 intel_private.registers+I810_PTE_BASE+(j*4));
960 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
977 if (pg_start < intel_private.gtt_entries) {
978 dev_info(&intel_private.pcidev->dev,
984 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
986 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1002 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1017 intel_private.resource_valid = 1;
1018 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1022 intel_private.resource_valid = 1;
1023 intel_private.ifp_resource.start = temp;
1024 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1025 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1028 intel_private.resource_valid = 0;
1044 intel_private.resource_valid = 1;
1046 upper_32_bits(intel_private.ifp_resource.start));
1047 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1054 intel_private.resource_valid = 1;
1055 intel_private.ifp_resource.start = l64;
1056 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1057 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1060 intel_private.resource_valid = 0;
1067 if (intel_private.ifp_resource.start)
1074 intel_private.ifp_resource.name = "Intel Flush Page";
1075 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1084 if (intel_private.ifp_resource.start)
1085 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1086 if (!intel_private.i9xx_flush_page)
1087 dev_err(&intel_private.pcidev->dev,
1100 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1108 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1109 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1112 for (i = intel_private.gtt_entries; i < intel_private.gtt_total_size; i++) {
1113 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1115 readl(intel_private.gtt+i-1); /* PCI Posting. */
1127 if (intel_private.i9xx_flush_page)
1128 iounmap(intel_private.i9xx_flush_page);
1129 if (intel_private.resource_valid)
1130 release_resource(&intel_private.ifp_resource);
1131 intel_private.ifp_resource.start = 0;
1132 intel_private.resource_valid = 0;
1133 iounmap(intel_private.gtt);
1134 iounmap(intel_private.registers);
1139 if (intel_private.i9xx_flush_page)
1140 writel(1, intel_private.i9xx_flush_page);
1157 if (pg_start < intel_private.gtt_entries) {
1158 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1159 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1160 pg_start, intel_private.gtt_entries);
1162 dev_info(&intel_private.pcidev->dev,
1203 if (pg_start < intel_private.gtt_entries) {
1204 dev_info(&intel_private.pcidev->dev,
1210 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1212 readl(intel_private.gtt+i-1);
1227 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1245 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
1267 dev_info(&intel_private.pcidev->dev,
1297 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1298 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1302 intel_private.registers = ioremap(temp, 128 * 4096);
1303 if (!intel_private.registers) {
1304 iounmap(intel_private.gtt);
1310 intel_private.gtt = ioremap(temp2, gtt_map_size);
1311 if (!intel_private.gtt)
1314 intel_private.gtt_total_size = gtt_map_size / 4;
1316 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1321 if (intel_private.gtt_entries == 0) {
1322 iounmap(intel_private.gtt);
1323 iounmap(intel_private.registers);
1385 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1421 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1427 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1429 if (!intel_private.gtt)
1432 intel_private.gtt_total_size = gtt_size / 4;
1434 intel_private.registers = ioremap(temp, 128 * 4096);
1435 if (!intel_private.registers) {
1436 iounmap(intel_private.gtt);
1440 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1445 if (intel_private.gtt_entries == 0) {
1446 iounmap(intel_private.gtt);
1447 iounmap(intel_private.registers);