Lines Matching defs:iadev
73 static void desc_dbg(IADEV *iadev);
519 IADEV *iadev;
523 iadev = INPH_IA_DEV(vcc->dev);
524 iadev->NumEnabledCBR--;
525 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);
526 if (iadev->NumEnabledCBR == 0) {
527 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
531 for (i=0; i < iadev->CbrTotEntries; i++)
534 iadev->CbrRemEntries++;
543 static int ia_avail_descs(IADEV *iadev) {
545 ia_hack_tcq(iadev);
546 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd)
547 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2;
549 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr -
550 iadev->ffL.tcq_st) / 2;
556 static int ia_que_tx (IADEV *iadev) {
561 num_desc = ia_avail_descs(iadev);
563 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) {
576 skb_queue_head(&iadev->tx_backlog, skb);
583 static void ia_tx_poll (IADEV *iadev) {
589 ia_hack_tcq(iadev);
590 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) {
628 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);
640 ia_que_tx(iadev);
645 static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
669 static void ia_hw_type(IADEV *iadev) {
670 u_short memType = ia_eeprom_get(iadev, 25);
671 iadev->memType = memType;
673 iadev->num_tx_desc = IA_TX_BUF;
674 iadev->tx_buf_sz = IA_TX_BUF_SZ;
675 iadev->num_rx_desc = IA_RX_BUF;
676 iadev->rx_buf_sz = IA_RX_BUF_SZ;
679 iadev->num_tx_desc = IA_TX_BUF / 2;
681 iadev->num_tx_desc = IA_TX_BUF;
682 iadev->tx_buf_sz = IA_TX_BUF_SZ;
684 iadev->num_rx_desc = IA_RX_BUF / 2;
686 iadev->num_rx_desc = IA_RX_BUF;
687 iadev->rx_buf_sz = IA_RX_BUF_SZ;
691 iadev->num_tx_desc = IA_TX_BUF / 8;
693 iadev->num_tx_desc = IA_TX_BUF;
694 iadev->tx_buf_sz = IA_TX_BUF_SZ;
696 iadev->num_rx_desc = IA_RX_BUF / 8;
698 iadev->num_rx_desc = IA_RX_BUF;
699 iadev->rx_buf_sz = IA_RX_BUF_SZ;
701 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
703 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
704 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
707 iadev->phy_type = memType & FE_MASK;
708 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
709 memType,iadev->phy_type);)
710 if (iadev->phy_type == FE_25MBIT_PHY)
711 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
712 else if (iadev->phy_type == FE_DS3_PHY)
713 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
714 else if (iadev->phy_type == FE_E3_PHY)
715 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
717 iadev->LineRate = (u32)(ATM_OC3_PCR);
718 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
722 static void IaFrontEndIntr(IADEV *iadev) {
729 if(iadev->phy_type & FE_25MBIT_PHY) {
730 mb25 = (ia_mb25_t*)iadev->phy;
731 iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB);
732 } else if (iadev->phy_type & FE_DS3_PHY) {
733 suni_pm7345 = (suni_pm7345_t *)iadev->phy;
736 iadev->carrier_detect =
738 } else if (iadev->phy_type & FE_E3_PHY ) {
739 suni_pm7345 = (suni_pm7345_t *)iadev->phy;
741 iadev->carrier_detect =
745 suni = (IA_SUNI *)iadev->phy;
747 iadev->carrier_detect = Boolean(!(suni->suni_rsop_status & SUNI_LOSV));
749 if (iadev->carrier_detect)
756 static void ia_mb25_init (IADEV *iadev)
758 volatile ia_mb25_t *mb25 = (ia_mb25_t*)iadev->phy;
764 iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB);
768 static void ia_suni_pm7345_init (IADEV *iadev)
770 volatile suni_pm7345_t *suni_pm7345 = (suni_pm7345_t *)iadev->phy;
771 if (iadev->phy_type & FE_DS3_PHY)
773 iadev->carrier_detect =
784 iadev->carrier_detect =
890 RAM_BASE*((iadev->mem)/(128 * 1024))
892 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
894 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
899 static void desc_dbg(IADEV *iadev) {
905 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
907 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
908 readw(iadev->seg_ram+tcq_wr_ptr-2));
909 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
910 iadev->ffL.tcq_rd);
911 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
912 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
916 tmp = iadev->seg_ram+tcq_st_ptr;
920 for(i=0; i <iadev->num_tx_desc; i++)
921 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
933 IADEV *iadev;
934 iadev = INPH_IA_DEV(dev);
935 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
936 iadev->rfL.fdq_wr +=2;
937 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
938 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
939 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
945 IADEV *iadev;
955 iadev = INPH_IA_DEV(dev);
956 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
962 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
963 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
964 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
966 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
968 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
969 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
971 iadev->rfL.pcq_rd += 2;
972 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
977 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
980 if (!desc || (desc > iadev->num_rx_desc) ||
981 ((buf_desc_ptr->vc_index & 0xffff) > iadev->num_vc)) {
986 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1020 if (len > iadev->rx_buf_sz) {
1021 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1035 skb_queue_tail(&iadev->rx_dma_q, skb);
1038 wr_ptr = iadev->rx_dle_q.write;
1039 wr_ptr->sys_pkt_addr = pci_map_single(iadev->pci, skb->data,
1046 if(++wr_ptr == iadev->rx_dle_q.end)
1047 wr_ptr = iadev->rx_dle_q.start;
1048 iadev->rx_dle_q.write = wr_ptr;
1051 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1060 IADEV *iadev;
1064 iadev = INPH_IA_DEV(dev);
1065 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1075 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1080 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1082 iadev->rxing = 1;
1086 if (iadev->rxing) {
1087 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1088 iadev->rx_tmp_jif = jiffies;
1089 iadev->rxing = 0;
1091 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1092 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1093 for (i = 1; i <= iadev->num_rx_desc; i++)
1096 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1097 iadev->rxing = 1;
1122 IADEV *iadev;
1130 iadev = INPH_IA_DEV(dev);
1137 dle = iadev->rx_dle_q.read;
1138 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1139 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1143 skb = skb_dequeue(&iadev->rx_dma_q);
1160 pci_unmap_single(iadev->pci, iadev->rx_dle_q.write->sys_pkt_addr,
1181 if ((length > iadev->rx_buf_sz) || (length >
1201 iadev->rx_pkt_cnt++;
1204 if (++dle == iadev->rx_dle_q.end)
1205 dle = iadev->rx_dle_q.start;
1207 iadev->rx_dle_q.read = dle;
1211 if (!iadev->rxing) {
1212 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1214 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1216 iadev->reass_reg+REASS_MASK_REG);
1217 iadev->rxing++;
1225 IADEV *iadev;
1228 IF_EVENT(printk("iadev: open_rx %d.%d\n", vcc->vpi, vcc->vci);)
1231 iadev = INPH_IA_DEV(vcc->dev);
1233 if (iadev->phy_type & FE_25MBIT_PHY) {
1240 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1251 init_abr_vc(iadev, &srv_p);
1252 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1255 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1260 if (iadev->rx_open[vcc->vci])
1263 iadev->rx_open[vcc->vci] = vcc;
1269 IADEV *iadev;
1280 iadev = INPH_IA_DEV(dev);
1281 // spin_lock_init(&iadev->rx_lock);
1284 dle_addr = pci_alloc_consistent(iadev->pci, DLE_TOTAL_SIZE,
1285 &iadev->rx_dle_dma);
1290 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1291 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1292 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1293 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1299 writel(iadev->rx_dle_dma & 0xfffff000,
1300 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1302 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1303 *(u32*)(iadev->dma+IPHASE5575_TX_LIST_ADDR));
1305 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1306 *(u32*)(iadev->dma+IPHASE5575_RX_LIST_ADDR));)
1308 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1309 writew(0, iadev->reass_reg+MODE_REG);
1310 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1326 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1328 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1331 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1332 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1335 rx_pkt_start = iadev->rx_pkt_ram;
1336 for(i=1; i<=iadev->num_rx_desc; i++)
1342 rx_pkt_start += iadev->rx_buf_sz;
1345 i = FREE_BUF_DESC_Q*iadev->memSize;
1346 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1347 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1348 writew(i+iadev->num_rx_desc*sizeof(u_short),
1349 iadev->reass_reg+FREEQ_ED_ADR);
1350 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1351 writew(i+iadev->num_rx_desc*sizeof(u_short),
1352 iadev->reass_reg+FREEQ_WR_PTR);
1354 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1355 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1356 for(i=1; i<=iadev->num_rx_desc; i++)
1363 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1364 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1365 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1366 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1367 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1370 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1371 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1373 iadev->reass_reg+EXCP_Q_ED_ADR);
1374 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1375 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1378 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1379 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1380 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1381 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1382 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1383 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1384 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1385 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1388 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1389 iadev->rfL.pcq_wr);)
1392 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1399 i = REASS_TABLE * iadev->memSize;
1400 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1402 reass_table = (u16 *)(iadev->reass_ram+i);
1403 j = REASS_TABLE_SZ * iadev->memSize;
1408 while (i != iadev->num_vc) {
1412 i = RX_VC_TABLE * iadev->memSize;
1413 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1414 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1415 j = RX_VC_TABLE_SZ * iadev->memSize;
1427 i = ABR_VC_TABLE * iadev->memSize;
1428 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1430 i = ABR_VC_TABLE * iadev->memSize;
1431 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1432 j = REASS_TABLE_SZ * iadev->memSize;
1443 writew(0xff00, iadev->reass_reg+VP_FILTER);
1444 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1445 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1451 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1456 writew(i, iadev->reass_reg+TMOUT_RANGE);
1459 for(i=0; i<iadev->num_tx_desc;i++)
1460 iadev->desc_tbl[i].timestamp = 0;
1463 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1466 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1468 skb_queue_head_init(&iadev->rx_dma_q);
1469 iadev->rx_free_desc_qhead = NULL;
1471 iadev->rx_open = kzalloc(4 * iadev->num_vc, GFP_KERNEL);
1472 if (!iadev->rx_open) {
1478 iadev->rxing = 1;
1479 iadev->rx_pkt_cnt = 0;
1481 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1485 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1486 iadev->rx_dle_dma);
1509 IADEV *iadev;
1513 iadev = INPH_IA_DEV(dev);
1515 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1519 spin_lock_irqsave(&iadev->tx_lock, flags);
1520 ia_tx_poll(iadev);
1521 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1522 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1523 if (iadev->close_pending)
1524 wake_up(&iadev->close_wait);
1534 IADEV *iadev;
1542 iadev = INPH_IA_DEV(dev);
1543 spin_lock_irqsave(&iadev->tx_lock, flags);
1544 dle = iadev->tx_dle_q.read;
1545 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1547 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1551 skb = skb_dequeue(&iadev->tx_dma_q);
1555 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1556 pci_unmap_single(iadev->pci, dle->sys_pkt_addr, skb->len,
1562 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1570 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1574 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1588 if (++dle == iadev->tx_dle_q.end)
1589 dle = iadev->tx_dle_q.start;
1591 iadev->tx_dle_q.read = dle;
1592 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1598 IADEV *iadev;
1602 IF_EVENT(printk("iadev: open_tx entered vcc->vci = %d\n", vcc->vci);)
1604 iadev = INPH_IA_DEV(vcc->dev);
1606 if (iadev->phy_type & FE_25MBIT_PHY) {
1619 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1621 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1631 vcc->qos.txtp.pcr = iadev->LineRate;
1633 vcc->qos.txtp.pcr = iadev->LineRate;
1636 if (vcc->qos.txtp.pcr > iadev->LineRate)
1637 vcc->qos.txtp.pcr = iadev->LineRate;
1640 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1641 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1644 if (ia_vcc->pcr < iadev->rate_limit)
1646 if (ia_vcc->pcr < iadev->rate_limit) {
1661 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1662 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1681 vc->acr = cellrate_to_float(iadev->LineRate);
1690 init_abr_vc(iadev, &srv_p);
1694 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1695 if (tmpsum > iadev->LineRate)
1698 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1723 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1725 if (iadev->phy_type & FE_25MBIT_PHY) {
1729 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1735 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1740 printk("iadev: Non UBR, ABR and CBR traffic not supportedn");
1742 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1750 IADEV *iadev;
1764 iadev = INPH_IA_DEV(dev);
1765 spin_lock_init(&iadev->tx_lock);
1768 readw(iadev->seg_reg+SEG_MASK_REG));)
1771 dle_addr = pci_alloc_consistent(iadev->pci, DLE_TOTAL_SIZE,
1772 &iadev->tx_dle_dma);
1777 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1778 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1779 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1780 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1783 writel(iadev->tx_dle_dma & 0xfffff000,
1784 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1785 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1786 writew(0, iadev->seg_reg+MODE_REG_0);
1787 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1788 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1789 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1790 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1812 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1815 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1819 for(i=1; i<=iadev->num_tx_desc; i++)
1826 tx_pkt_start += iadev->tx_buf_sz;
1828 iadev->tx_buf = kmalloc(iadev->num_tx_desc*sizeof(struct cpcs_trailer_desc), GFP_KERNEL);
1829 if (!iadev->tx_buf) {
1833 for (i= 0; i< iadev->num_tx_desc; i++)
1842 iadev->tx_buf[i].cpcs = cpcs;
1843 iadev->tx_buf[i].dma_addr = pci_map_single(iadev->pci,
1846 iadev->desc_tbl = kmalloc(iadev->num_tx_desc *
1848 if (!iadev->desc_tbl) {
1854 i = TX_COMP_Q * iadev->memSize;
1855 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
1858 writew(i, iadev->seg_reg+TCQ_ST_ADR);
1859 writew(i, iadev->seg_reg+TCQ_RD_PTR);
1860 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
1861 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
1862 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
1863 iadev->seg_reg+TCQ_ED_ADR);
1865 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
1866 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
1867 for(i=1; i<=iadev->num_tx_desc; i++)
1874 i = PKT_RDY_Q * iadev->memSize;
1875 writew(i, iadev->seg_reg+PRQ_ST_ADR);
1876 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
1877 iadev->seg_reg+PRQ_ED_ADR);
1878 writew(i, iadev->seg_reg+PRQ_RD_PTR);
1879 writew(i, iadev->seg_reg+PRQ_WR_PTR);
1882 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
1883 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
1884 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
1886 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
1887 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
1888 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
1892 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
1893 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
1894 for(i=1; i<=iadev->num_tx_desc; i++)
1901 writew(0,iadev->seg_reg+CBR_PTR_BASE);
1904 readw(iadev->seg_reg+CBR_PTR_BASE));)
1905 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
1906 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
1908 readw(iadev->seg_reg+CBR_TAB_BEG));)
1909 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
1910 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
1911 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
1912 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
1913 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
1915 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
1916 readw(iadev->seg_reg+CBR_TAB_END+1));)
1919 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
1920 0, iadev->num_vc*6);
1921 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
1922 iadev->CbrEntryPt = 0;
1923 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
1924 iadev->NumEnabledCBR = 0;
1937 while (i != iadev->num_vc) {
1942 i = MAIN_VC_TABLE * iadev->memSize;
1943 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
1944 i = EXT_VC_TABLE * iadev->memSize;
1945 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
1946 i = UBR_SCHED_TABLE * iadev->memSize;
1947 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
1948 i = UBR_WAIT_Q * iadev->memSize;
1949 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
1950 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
1951 0, iadev->num_vc*8);
1960 i = ABR_SCHED_TABLE * iadev->memSize;
1961 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
1962 i = ABR_WAIT_Q * iadev->memSize;
1963 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
1965 i = ABR_SCHED_TABLE*iadev->memSize;
1966 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
1967 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1968 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1969 iadev->testTable = kmalloc(sizeof(long)*iadev->num_vc, GFP_KERNEL);
1970 if (!iadev->testTable) {
1974 for(i=0; i<iadev->num_vc; i++)
1978 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
1980 if (!iadev->testTable[i])
1982 iadev->testTable[i]->lastTime = 0;
1983 iadev->testTable[i]->fract = 0;
1984 iadev->testTable[i]->vc_status = VC_UBR;
1992 if (iadev->phy_type & FE_25MBIT_PHY) {
1993 writew(RATE25, iadev->seg_reg+MAXRATE);
1994 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
1997 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
1998 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2001 writew(0, iadev->seg_reg+IDLEHEADHI);
2002 writew(0, iadev->seg_reg+IDLEHEADLO);
2005 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2007 iadev->close_pending = 0;
2008 init_waitqueue_head(&iadev->close_wait);
2009 init_waitqueue_head(&iadev->timeout_wait);
2010 skb_queue_head_init(&iadev->tx_dma_q);
2011 ia_init_rtn_q(&iadev->tx_return_q);
2014 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2015 skb_queue_head_init (&iadev->tx_backlog);
2018 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2021 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2024 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2027 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2028 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2029 iadev->tx_pkt_cnt = 0;
2030 iadev->rate_limit = iadev->LineRate / 3;
2036 kfree(iadev->testTable[i]);
2037 kfree(iadev->testTable);
2039 kfree(iadev->desc_tbl);
2041 i = iadev->num_tx_desc;
2044 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2046 pci_unmap_single(iadev->pci, desc->dma_addr,
2050 kfree(iadev->tx_buf);
2052 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2053 iadev->tx_dle_dma);
2061 IADEV *iadev;
2066 iadev = INPH_IA_DEV(dev);
2067 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2080 *(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLERINT;
2091 *(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLETINT;
2097 IaFrontEndIntr(iadev);
2108 IADEV *iadev;
2113 iadev = INPH_IA_DEV(dev);
2115 iadev->reg+IPHASE5575_MAC1)));
2116 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2128 IADEV *iadev;
2132 iadev = INPH_IA_DEV(dev);
2134 if ((error = pci_read_config_dword(iadev->pci,
2137 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2139 if ((error = pci_write_config_dword(iadev->pci,
2149 IADEV *iadev;
2163 iadev = INPH_IA_DEV(dev);
2164 real_base = pci_resource_start (iadev->pci, 0);
2165 iadev->irq = iadev->pci->irq;
2167 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2174 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2178 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2180 if (iadev->pci_map_size == 0x100000){
2181 iadev->num_vc = 4096;
2183 iadev->memSize = 4;
2185 else if (iadev->pci_map_size == 0x40000) {
2186 iadev->num_vc = 1024;
2187 iadev->memSize = 1;
2190 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2193 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2196 pci_set_master(iadev->pci);
2204 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2213 dev->number, iadev->pci->revision, base, iadev->irq);)
2216 iadev->mem = iadev->pci_map_size /2;
2217 iadev->real_base = real_base;
2218 iadev->base = base;
2221 iadev->reg = base + REG_BASE;
2223 iadev->seg_reg = base + SEG_BASE;
2225 iadev->reass_reg = base + REASS_BASE;
2227 iadev->phy = base + PHY_BASE;
2228 iadev->dma = base + PHY_BASE;
2230 iadev->ram = base + ACTUAL_RAM_BASE;
2231 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2232 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2236 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2237 iadev->phy, iadev->ram, iadev->seg_ram,
2238 iadev->reass_ram);)
2243 iounmap(iadev->base);
2253 iounmap(iadev->base);
2260 static void ia_update_stats(IADEV *iadev) {
2261 if (!iadev->carrier_detect)
2263 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2264 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2265 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2266 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2267 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2268 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2313 static void ia_free_tx(IADEV *iadev)
2317 kfree(iadev->desc_tbl);
2318 for (i = 0; i < iadev->num_vc; i++)
2319 kfree(iadev->testTable[i]);
2320 kfree(iadev->testTable);
2321 for (i = 0; i < iadev->num_tx_desc; i++) {
2322 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2324 pci_unmap_single(iadev->pci, desc->dma_addr,
2328 kfree(iadev->tx_buf);
2329 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2330 iadev->tx_dle_dma);
2333 static void ia_free_rx(IADEV *iadev)
2335 kfree(iadev->rx_open);
2336 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2337 iadev->rx_dle_dma);
2342 IADEV *iadev;
2347 iadev = INPH_IA_DEV(dev);
2348 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2350 dev->number, iadev->irq);
2356 if ((error = pci_write_config_word(iadev->pci,
2371 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2372 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2388 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2391 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2393 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2395 ia_hw_type(iadev);
2403 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2404 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2406 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2414 if (iadev->phy_type & FE_25MBIT_PHY)
2415 ia_mb25_init(iadev);
2416 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2417 ia_suni_pm7345_init(iadev);
2427 /* Get iadev->carrier_detect status */
2428 IaFrontEndIntr(iadev);
2433 ia_free_rx(iadev);
2435 ia_free_tx(iadev);
2437 free_irq(iadev->irq, dev);
2446 IADEV *iadev;
2452 iadev = INPH_IA_DEV(vcc->dev);
2462 iadev->close_pending++;
2463 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2465 finish_wait(&iadev->timeout_wait, &wait);
2466 spin_lock_irqsave(&iadev->tx_lock, flags);
2467 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2476 skb_queue_tail(&iadev->tx_backlog, skb);
2481 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2482 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2483 spin_lock_irqsave(&iadev->tx_lock, flags);
2484 iadev->close_pending--;
2485 iadev->testTable[vcc->vci]->lastTime = 0;
2486 iadev->testTable[vcc->vci]->fract = 0;
2487 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2490 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2494 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2497 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2502 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2506 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2511 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2518 iadev->rx_open[vcc->vci] = NULL;
2529 IADEV *iadev;
2537 iadev = INPH_IA_DEV(vcc->dev);
2555 IF_EVENT(printk("iadev: error in open_rx, closing\n");)
2562 IF_EVENT(printk("iadev: error in open_tx, closing\n");)
2582 IADEV *iadev;
2594 iadev = ia_dev[board];
2601 if (copy_to_user(ia_cmds.buf, iadev, sizeof(IADEV)))
2609 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2617 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2634 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2637 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2651 desc_dbg(iadev);
2658 printk("skb = 0x%lx\n", (long)skb_peek(&iadev->tx_backlog));
2659 printk("rtn_q: 0x%lx\n",(long)ia_deque_rtn_q(&iadev->tx_return_q));
2680 for (i = 1; i <= iadev->num_rx_desc; i++)
2683 iadev->reass_reg+REASS_MASK_REG);
2684 iadev->rxing = 1;
2691 IaFrontEndIntr(iadev);
2729 IADEV *iadev;
2738 iadev = INPH_IA_DEV(vcc->dev);
2749 if (skb->len > iadev->tx_buf_sz - 8) {
2770 desc = get_desc (iadev, iavcc);
2776 if ((desc == 0) || (desc > iadev->num_tx_desc))
2795 iadev->desc_tbl[desc-1].iavcc = iavcc;
2796 iadev->desc_tbl[desc-1].txskb = skb;
2799 iadev->ffL.tcq_rd += 2;
2800 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2801 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2802 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2807 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2809 iadev->ffL.prq_wr += 2;
2810 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2811 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2820 trailer = iadev->tx_buf[desc-1].cpcs;
2835 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
2839 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2844 clear_lockup (vcc, iadev);
2847 wr_ptr = iadev->tx_dle_q.write;
2849 wr_ptr->sys_pkt_addr = pci_map_single(iadev->pci, skb->data,
2864 if (++wr_ptr == iadev->tx_dle_q.end)
2865 wr_ptr = iadev->tx_dle_q.start;
2868 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
2874 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
2877 if (++wr_ptr == iadev->tx_dle_q.end)
2878 wr_ptr = iadev->tx_dle_q.start;
2880 iadev->tx_dle_q.write = wr_ptr;
2882 skb_queue_tail(&iadev->tx_dma_q, skb);
2885 iadev->tx_pkt_cnt++;
2887 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
2895 IADEV *iadev;
2899 iadev = INPH_IA_DEV(vcc->dev);
2901 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
2908 spin_lock_irqsave(&iadev->tx_lock, flags);
2911 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2916 if (skb_peek(&iadev->tx_backlog)) {
2917 skb_queue_tail(&iadev->tx_backlog, skb);
2921 skb_queue_tail(&iadev->tx_backlog, skb);
2924 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2933 IADEV *iadev = INPH_IA_DEV(dev);
2935 if (iadev->phy_type == FE_25MBIT_PHY) {
2939 if (iadev->phy_type == FE_DS3_PHY)
2941 else if (iadev->phy_type == FE_E3_PHY)
2943 else if (iadev->phy_type == FE_UTP_OPTION)
2948 if (iadev->pci_map_size == 0x40000)
2953 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
2955 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
2972 iadev->num_tx_desc, iadev->tx_buf_sz,
2973 iadev->num_rx_desc, iadev->rx_buf_sz,
2974 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
2975 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
2976 iadev->drop_rxcell, iadev->drop_rxpkt);
2999 IADEV *iadev;
3002 iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
3003 if (!iadev) {
3008 iadev->pci = pdev;
3021 dev->dev_data = iadev;
3023 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3024 iadev->LineRate);)
3028 ia_dev[iadev_count] = iadev;
3041 iadev->next_board = ia_boards;
3051 kfree(iadev);
3059 IADEV *iadev = INPH_IA_DEV(dev);
3070 free_irq(iadev->irq, dev);
3077 iounmap(iadev->base);
3080 ia_free_rx(iadev);
3081 ia_free_tx(iadev);
3083 kfree(iadev);