Lines Matching refs:he_writel
176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
185 he_writel(he_dev, val, CON_DAT);
187 he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
203 he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
459 he_writel(he_dev, lbufd_index, RLBF0_H);
475 he_writel(he_dev, lbufd_index - 2, RLBF0_T);
476 he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
490 he_writel(he_dev, lbufd_index, RLBF1_H);
506 he_writel(he_dev, lbufd_index - 2, RLBF1_T);
507 he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
521 he_writel(he_dev, lbufd_index, TLBF_H);
537 he_writel(he_dev, lbufd_index - 1, TLBF_T);
555 he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
556 he_writel(he_dev, 0, TPDRQ_T);
557 he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
786 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
787 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
788 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
789 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
843 he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
844 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
846 he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
848 he_writel(he_dev,
865 he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
866 he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
867 he_writel(he_dev,
872 he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
875 he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
890 he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
891 he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
892 he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
893 he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
941 he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
942 he_writel(he_dev,
945 he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
946 he_writel(he_dev, 0x0, IRQ0_DATA);
948 he_writel(he_dev, 0x0, IRQ1_BASE);
949 he_writel(he_dev, 0x0, IRQ1_HEAD);
950 he_writel(he_dev, 0x0, IRQ1_CNTL);
951 he_writel(he_dev, 0x0, IRQ1_DATA);
953 he_writel(he_dev, 0x0, IRQ2_BASE);
954 he_writel(he_dev, 0x0, IRQ2_HEAD);
955 he_writel(he_dev, 0x0, IRQ2_CNTL);
956 he_writel(he_dev, 0x0, IRQ2_DATA);
958 he_writel(he_dev, 0x0, IRQ3_BASE);
959 he_writel(he_dev, 0x0, IRQ3_HEAD);
960 he_writel(he_dev, 0x0, IRQ3_CNTL);
961 he_writel(he_dev, 0x0, IRQ3_DATA);
965 he_writel(he_dev, 0x0, GRP_10_MAP);
966 he_writel(he_dev, 0x0, GRP_32_MAP);
967 he_writel(he_dev, 0x0, GRP_54_MAP);
968 he_writel(he_dev, 0x0, GRP_76_MAP);
1066 he_writel(he_dev, 0x0, RESET_CNTL);
1067 he_writel(he_dev, 0xff, RESET_CNTL);
1126 he_writel(he_dev, lb_swap, LB_SWAP);
1129 he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
1133 he_writel(he_dev, lb_swap, LB_SWAP);
1142 he_writel(he_dev, host_cntl, HOST_CNTL);
1240 he_writel(he_dev,
1247 he_writel(he_dev, BANK_ON |
1251 he_writel(he_dev,
1254 he_writel(he_dev,
1258 he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
1260 he_writel(he_dev,
1266 he_writel(he_dev, DRF_THRESH(0x20) |
1271 he_writel(he_dev, 0x0, TXAAL5_PROTO);
1273 he_writel(he_dev, PHY_INT_ENB |
1316 he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
1317 he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
1318 he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
1319 he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
1320 he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
1350 he_writel(he_dev, 0x08000, RCMLBM_BA);
1351 he_writel(he_dev, 0x0e000, RCMRSRB_BA);
1352 he_writel(he_dev, 0x0d800, RCMABR_BA);
1359 he_writel(he_dev, 0x0, RLBC_H);
1360 he_writel(he_dev, 0x0, RLBC_T);
1361 he_writel(he_dev, 0x0, RLBC_H2);
1363 he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */
1364 he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */
1368 he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
1373 he_writel(he_dev, 0x000f, G0_INMQ_S);
1374 he_writel(he_dev, 0x200f, G0_INMQ_L);
1376 he_writel(he_dev, 0x001f, G1_INMQ_S);
1377 he_writel(he_dev, 0x201f, G1_INMQ_L);
1379 he_writel(he_dev, 0x002f, G2_INMQ_S);
1380 he_writel(he_dev, 0x202f, G2_INMQ_L);
1382 he_writel(he_dev, 0x003f, G3_INMQ_S);
1383 he_writel(he_dev, 0x203f, G3_INMQ_L);
1385 he_writel(he_dev, 0x004f, G4_INMQ_S);
1386 he_writel(he_dev, 0x204f, G4_INMQ_L);
1388 he_writel(he_dev, 0x005f, G5_INMQ_S);
1389 he_writel(he_dev, 0x205f, G5_INMQ_L);
1391 he_writel(he_dev, 0x006f, G6_INMQ_S);
1392 he_writel(he_dev, 0x206f, G6_INMQ_L);
1394 he_writel(he_dev, 0x007f, G7_INMQ_S);
1395 he_writel(he_dev, 0x207f, G7_INMQ_L);
1397 he_writel(he_dev, 0x0000, G0_INMQ_S);
1398 he_writel(he_dev, 0x0008, G0_INMQ_L);
1400 he_writel(he_dev, 0x0001, G1_INMQ_S);
1401 he_writel(he_dev, 0x0009, G1_INMQ_L);
1403 he_writel(he_dev, 0x0002, G2_INMQ_S);
1404 he_writel(he_dev, 0x000a, G2_INMQ_L);
1406 he_writel(he_dev, 0x0003, G3_INMQ_S);
1407 he_writel(he_dev, 0x000b, G3_INMQ_L);
1409 he_writel(he_dev, 0x0004, G4_INMQ_S);
1410 he_writel(he_dev, 0x000c, G4_INMQ_L);
1412 he_writel(he_dev, 0x0005, G5_INMQ_S);
1413 he_writel(he_dev, 0x000d, G5_INMQ_L);
1415 he_writel(he_dev, 0x0006, G6_INMQ_S);
1416 he_writel(he_dev, 0x000e, G6_INMQ_L);
1418 he_writel(he_dev, 0x0007, G7_INMQ_S);
1419 he_writel(he_dev, 0x000f, G7_INMQ_L);
1424 he_writel(he_dev, 0x0, MCC);
1425 he_writel(he_dev, 0x0, OEC);
1426 he_writel(he_dev, 0x0, DCC);
1427 he_writel(he_dev, 0x0, CEC);
1455 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
1456 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
1457 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
1458 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1461 he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
1462 he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
1463 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1465 he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
1467 he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
1468 he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
1469 he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
1471 he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
1473 he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
1474 he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
1475 he_writel(he_dev, TBRQ_THRESH(0x1),
1477 he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
1489 he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
1518 he_writel(he_dev, reg, RC_CONFIG);
1569 he_writel(he_dev, reg, RC_CONFIG);
1813 he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
1894 he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
1943 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
2024 he_writel(he_dev,
2063 he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */
2126 he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
2695 he_writel(he_dev, val, FRAMER + (addr*4));
2812 he_writel(he_dev, val, HOST_CNTL);
2816 he_writel(he_dev, val | readtab[i], HOST_CNTL);
2822 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2824 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2831 he_writel(he_dev, val, HOST_CNTL);
2835 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2840 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2844 he_writel(he_dev, val | ID_CS, HOST_CNTL);