Lines Matching refs:he_dev
88 #define hprintk(fmt,args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
91 #define HPRINTK(fmt,args...) printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
106 static void he_stop(struct he_dev *dev);
110 static u8 read_prom_byte(struct he_dev *he_dev, int addr);
114 static struct he_dev *he_devs;
182 he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
185 he_writel(he_dev, val, CON_DAT);
186 (void) he_readl(he_dev, CON_DAT); /* flush posted writes */
187 he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
188 while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
201 he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)
203 he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
204 while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
205 return he_readl(he_dev, CON_DAT);
328 __find_vcc(struct he_dev *he_dev, unsigned cid)
337 vpi = cid >> he_dev->vcibits;
338 vci = cid & ((1 << he_dev->vcibits) - 1);
343 if (vcc->dev == he_dev->atm_dev &&
356 struct he_dev *he_dev = NULL;
376 he_dev = kzalloc(sizeof(struct he_dev),
378 if (!he_dev) {
382 he_dev->pci_dev = pci_dev;
383 he_dev->atm_dev = atm_dev;
384 he_dev->atm_dev->dev_data = he_dev;
385 atm_dev->dev_data = he_dev;
386 he_dev->number = atm_dev->number;
387 tasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);
388 spin_lock_init(&he_dev->global_lock);
391 he_stop(he_dev);
395 he_dev->next = NULL;
397 he_dev->next = he_devs;
398 he_devs = he_dev;
404 kfree(he_dev);
413 struct he_dev *he_dev;
416 he_dev = HE_DEV(atm_dev);
420 he_stop(he_dev);
422 kfree(he_dev);
449 he_init_rx_lbfp0(struct he_dev *he_dev)
452 unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
453 unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
454 unsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;
457 lbm_offset = he_readl(he_dev, RCMLBM_BA);
459 he_writel(he_dev, lbufd_index, RLBF0_H);
461 for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {
465 he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
466 he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
470 row_offset += he_dev->bytes_per_row;
475 he_writel(he_dev, lbufd_index - 2, RLBF0_T);
476 he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
480 he_init_rx_lbfp1(struct he_dev *he_dev)
483 unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
484 unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
485 unsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;
488 lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
490 he_writel(he_dev, lbufd_index, RLBF1_H);
492 for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {
496 he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
497 he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
501 row_offset += he_dev->bytes_per_row;
506 he_writel(he_dev, lbufd_index - 2, RLBF1_T);
507 he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
511 he_init_tx_lbfp(struct he_dev *he_dev)
514 unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
515 unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
516 unsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;
518 lbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;
519 lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
521 he_writel(he_dev, lbufd_index, TLBF_H);
523 for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {
527 he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
528 he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
532 row_offset += he_dev->bytes_per_row;
537 he_writel(he_dev, lbufd_index - 1, TLBF_T);
541 he_init_tpdrq(struct he_dev *he_dev)
543 he_dev->tpdrq_base = pci_alloc_consistent(he_dev->pci_dev,
544 CONFIG_TPDRQ_SIZE * sizeof(struct he_tpdrq), &he_dev->tpdrq_phys);
545 if (he_dev->tpdrq_base == NULL) {
549 memset(he_dev->tpdrq_base, 0,
552 he_dev->tpdrq_tail = he_dev->tpdrq_base;
553 he_dev->tpdrq_head = he_dev->tpdrq_base;
555 he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
556 he_writel(he_dev, 0, TPDRQ_T);
557 he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
563 he_init_cs_block(struct he_dev *he_dev)
571 he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);
575 clock = he_is622(he_dev) ? 66667000 : 50000000;
576 rate = he_dev->atm_dev->link_rate;
587 he_writel_mbox(he_dev, period, CS_TGRLD0 + reg);
591 if (he_is622(he_dev)) {
593 he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);
594 he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);
595 he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);
596 he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);
597 he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);
600 he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);
601 he_writel_mbox(he_dev, 0x1801, CS_ERCTL1);
602 he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);
603 he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
604 he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);
605 he_writel_mbox(he_dev, 0x14585, CS_RTFWR);
607 he_writel_mbox(he_dev, 0x4680, CS_RTATR);
610 he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);
611 he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);
612 he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);
613 he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);
614 he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);
615 he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);
618 he_writel_mbox(he_dev, 0x5, CS_OTPPER);
619 he_writel_mbox(he_dev, 0x14, CS_OTWPER);
622 he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);
623 he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);
624 he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);
625 he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);
626 he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);
629 he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);
630 he_writel_mbox(he_dev, 0x4701, CS_ERCTL1);
631 he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);
632 he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
633 he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);
634 he_writel_mbox(he_dev, 0xf424, CS_RTFWR);
636 he_writel_mbox(he_dev, 0x4680, CS_RTATR);
639 he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);
640 he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);
641 he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);
642 he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);
643 he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);
644 he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);
647 he_writel_mbox(he_dev, 0x6, CS_OTPPER);
648 he_writel_mbox(he_dev, 0x1e, CS_OTWPER);
651 he_writel_mbox(he_dev, 0x8, CS_OTTLIM);
654 he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);
659 he_init_cs_block_rcm(struct he_dev *he_dev)
676 he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
681 he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
691 rate = he_dev->atm_dev->link_rate;
746 buf = rate_cps * he_dev->tx_numbuffs /
747 (he_dev->atm_dev->link_rate * 2);
750 mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;
769 he_writel_rcm(he_dev, reg,
780 he_init_group(struct he_dev *he_dev, int group)
786 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
787 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
788 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
789 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
793 he_dev->rbpl_table = kmalloc(BITS_TO_LONGS(RBPL_TABLE_SIZE)
795 if (!he_dev->rbpl_table) {
799 bitmap_zero(he_dev->rbpl_table, RBPL_TABLE_SIZE);
802 he_dev->rbpl_virt = kmalloc(RBPL_TABLE_SIZE
804 if (!he_dev->rbpl_virt) {
810 he_dev->rbpl_pool = pci_pool_create("rbpl", he_dev->pci_dev,
812 if (he_dev->rbpl_pool == NULL) {
817 he_dev->rbpl_base = pci_alloc_consistent(he_dev->pci_dev,
818 CONFIG_RBPL_SIZE * sizeof(struct he_rbp), &he_dev->rbpl_phys);
819 if (he_dev->rbpl_base == NULL) {
823 memset(he_dev->rbpl_base, 0, CONFIG_RBPL_SIZE * sizeof(struct he_rbp));
825 INIT_LIST_HEAD(&he_dev->rbpl_outstanding);
829 heb = pci_pool_alloc(he_dev->rbpl_pool, GFP_KERNEL|GFP_DMA, &mapping);
833 list_add(&heb->entry, &he_dev->rbpl_outstanding);
835 set_bit(i, he_dev->rbpl_table);
836 he_dev->rbpl_virt[i] = heb;
837 he_dev->rbpl_hint = i + 1;
838 he_dev->rbpl_base[i].idx = i << RBP_IDX_OFFSET;
839 he_dev->rbpl_base[i].phys = mapping + offsetof(struct he_buff, data);
841 he_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];
843 he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
844 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
846 he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
848 he_writel(he_dev,
856 he_dev->rbrq_base = pci_alloc_consistent(he_dev->pci_dev,
857 CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq), &he_dev->rbrq_phys);
858 if (he_dev->rbrq_base == NULL) {
862 memset(he_dev->rbrq_base, 0, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq));
864 he_dev->rbrq_head = he_dev->rbrq_base;
865 he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
866 he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
867 he_writel(he_dev,
872 he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
875 he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
880 he_dev->tbrq_base = pci_alloc_consistent(he_dev->pci_dev,
881 CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq), &he_dev->tbrq_phys);
882 if (he_dev->tbrq_base == NULL) {
886 memset(he_dev->tbrq_base, 0, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq));
888 he_dev->tbrq_head = he_dev->tbrq_base;
890 he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
891 he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
892 he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
893 he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
898 pci_free_consistent(he_dev->pci_dev, CONFIG_RBRQ_SIZE *
899 sizeof(struct he_rbrq), he_dev->rbrq_base,
900 he_dev->rbrq_phys);
902 list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
903 pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
905 pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE *
906 sizeof(struct he_rbp), he_dev->rbpl_base,
907 he_dev->rbpl_phys);
909 pci_pool_destroy(he_dev->rbpl_pool);
911 kfree(he_dev->rbpl_virt);
913 kfree(he_dev->rbpl_table);
919 he_init_irq(struct he_dev *he_dev)
926 he_dev->irq_base = pci_alloc_consistent(he_dev->pci_dev,
927 (CONFIG_IRQ_SIZE+1) * sizeof(struct he_irq), &he_dev->irq_phys);
928 if (he_dev->irq_base == NULL) {
932 he_dev->irq_tailoffset = (unsigned *)
933 &he_dev->irq_base[CONFIG_IRQ_SIZE];
934 *he_dev->irq_tailoffset = 0;
935 he_dev->irq_head = he_dev->irq_base;
936 he_dev->irq_tail = he_dev->irq_base;
939 he_dev->irq_base[i].isw = ITYPE_INVALID;
941 he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
942 he_writel(he_dev,
945 he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
946 he_writel(he_dev, 0x0, IRQ0_DATA);
948 he_writel(he_dev, 0x0, IRQ1_BASE);
949 he_writel(he_dev, 0x0, IRQ1_HEAD);
950 he_writel(he_dev, 0x0, IRQ1_CNTL);
951 he_writel(he_dev, 0x0, IRQ1_DATA);
953 he_writel(he_dev, 0x0, IRQ2_BASE);
954 he_writel(he_dev, 0x0, IRQ2_HEAD);
955 he_writel(he_dev, 0x0, IRQ2_CNTL);
956 he_writel(he_dev, 0x0, IRQ2_DATA);
958 he_writel(he_dev, 0x0, IRQ3_BASE);
959 he_writel(he_dev, 0x0, IRQ3_HEAD);
960 he_writel(he_dev, 0x0, IRQ3_CNTL);
961 he_writel(he_dev, 0x0, IRQ3_DATA);
965 he_writel(he_dev, 0x0, GRP_10_MAP);
966 he_writel(he_dev, 0x0, GRP_32_MAP);
967 he_writel(he_dev, 0x0, GRP_54_MAP);
968 he_writel(he_dev, 0x0, GRP_76_MAP);
970 if (request_irq(he_dev->pci_dev->irq,
971 he_irq_handler, IRQF_SHARED, DEV_LABEL, he_dev)) {
972 hprintk("irq %d already in use\n", he_dev->pci_dev->irq);
976 he_dev->irq = he_dev->pci_dev->irq;
984 struct he_dev *he_dev;
996 he_dev = HE_DEV(dev);
997 pci_dev = he_dev->pci_dev;
1060 if (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) {
1066 he_writel(he_dev, 0x0, RESET_CNTL);
1067 he_writel(he_dev, 0xff, RESET_CNTL);
1070 status = he_readl(he_dev, RESET_CNTL);
1077 host_cntl = he_readl(he_dev, HOST_CNTL);
1095 he_dev->prod_id[i] = read_prom_byte(he_dev, PROD_ID + i);
1097 he_dev->media = read_prom_byte(he_dev, MEDIA);
1100 dev->esi[i] = read_prom_byte(he_dev, MAC_ADDR + i);
1103 he_dev->prod_id,
1104 he_dev->media & 0x40 ? "SM" : "MM",
1111 he_dev->atm_dev->link_rate = he_is622(he_dev) ?
1115 lb_swap = he_readl(he_dev, LB_SWAP);
1116 if (he_is622(he_dev))
1126 he_writel(he_dev, lb_swap, LB_SWAP);
1129 he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
1133 he_writel(he_dev, lb_swap, LB_SWAP);
1136 if ((err = he_init_irq(he_dev)) != 0)
1142 he_writel(he_dev, host_cntl, HOST_CNTL);
1182 he_dev->vcibits = CONFIG_DEFAULT_VCIBITS;
1183 he_dev->vpibits = CONFIG_DEFAULT_VPIBITS;
1191 he_dev->vpibits = nvpibits;
1192 he_dev->vcibits = HE_MAXCIDBITS - nvpibits;
1196 he_dev->vcibits = nvcibits;
1197 he_dev->vpibits = HE_MAXCIDBITS - nvcibits;
1201 if (he_is622(he_dev)) {
1202 he_dev->cells_per_row = 40;
1203 he_dev->bytes_per_row = 2048;
1204 he_dev->r0_numrows = 256;
1205 he_dev->tx_numrows = 512;
1206 he_dev->r1_numrows = 256;
1207 he_dev->r0_startrow = 0;
1208 he_dev->tx_startrow = 256;
1209 he_dev->r1_startrow = 768;
1211 he_dev->cells_per_row = 20;
1212 he_dev->bytes_per_row = 1024;
1213 he_dev->r0_numrows = 512;
1214 he_dev->tx_numrows = 1018;
1215 he_dev->r1_numrows = 512;
1216 he_dev->r0_startrow = 6;
1217 he_dev->tx_startrow = 518;
1218 he_dev->r1_startrow = 1536;
1221 he_dev->cells_per_lbuf = 4;
1222 he_dev->buffer_limit = 4;
1223 he_dev->r0_numbuffs = he_dev->r0_numrows *
1224 he_dev->cells_per_row / he_dev->cells_per_lbuf;
1225 if (he_dev->r0_numbuffs > 2560)
1226 he_dev->r0_numbuffs = 2560;
1228 he_dev->r1_numbuffs = he_dev->r1_numrows *
1229 he_dev->cells_per_row / he_dev->cells_per_lbuf;
1230 if (he_dev->r1_numbuffs > 2560)
1231 he_dev->r1_numbuffs = 2560;
1233 he_dev->tx_numbuffs = he_dev->tx_numrows *
1234 he_dev->cells_per_row / he_dev->cells_per_lbuf;
1235 if (he_dev->tx_numbuffs > 5120)
1236 he_dev->tx_numbuffs = 5120;
1240 he_writel(he_dev,
1243 (he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |
1244 (he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)),
1247 he_writel(he_dev, BANK_ON |
1248 (he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)),
1251 he_writel(he_dev,
1252 (he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |
1254 he_writel(he_dev,
1255 (he_is622(he_dev) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |
1258 he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
1260 he_writel(he_dev,
1261 (he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |
1262 (he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |
1263 RX_VALVP(he_dev->vpibits) |
1264 RX_VALVC(he_dev->vcibits), RC_CONFIG);
1266 he_writel(he_dev, DRF_THRESH(0x20) |
1267 (he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |
1268 TX_VCI_MASK(he_dev->vcibits) |
1269 LBFREE_CNT(he_dev->tx_numbuffs), TX_CONFIG);
1271 he_writel(he_dev, 0x0, TXAAL5_PROTO);
1273 he_writel(he_dev, PHY_INT_ENB |
1274 (he_is622(he_dev) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),
1280 he_writel_tcm(he_dev, 0, i);
1283 he_writel_rcm(he_dev, 0, i);
1316 he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
1317 he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
1318 he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
1319 he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
1320 he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
1350 he_writel(he_dev, 0x08000, RCMLBM_BA);
1351 he_writel(he_dev, 0x0e000, RCMRSRB_BA);
1352 he_writel(he_dev, 0x0d800, RCMABR_BA);
1356 he_init_rx_lbfp0(he_dev);
1357 he_init_rx_lbfp1(he_dev);
1359 he_writel(he_dev, 0x0, RLBC_H);
1360 he_writel(he_dev, 0x0, RLBC_T);
1361 he_writel(he_dev, 0x0, RLBC_H2);
1363 he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */
1364 he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */
1366 he_init_tx_lbfp(he_dev);
1368 he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
1372 if (he_is622(he_dev)) {
1373 he_writel(he_dev, 0x000f, G0_INMQ_S);
1374 he_writel(he_dev, 0x200f, G0_INMQ_L);
1376 he_writel(he_dev, 0x001f, G1_INMQ_S);
1377 he_writel(he_dev, 0x201f, G1_INMQ_L);
1379 he_writel(he_dev, 0x002f, G2_INMQ_S);
1380 he_writel(he_dev, 0x202f, G2_INMQ_L);
1382 he_writel(he_dev, 0x003f, G3_INMQ_S);
1383 he_writel(he_dev, 0x203f, G3_INMQ_L);
1385 he_writel(he_dev, 0x004f, G4_INMQ_S);
1386 he_writel(he_dev, 0x204f, G4_INMQ_L);
1388 he_writel(he_dev, 0x005f, G5_INMQ_S);
1389 he_writel(he_dev, 0x205f, G5_INMQ_L);
1391 he_writel(he_dev, 0x006f, G6_INMQ_S);
1392 he_writel(he_dev, 0x206f, G6_INMQ_L);
1394 he_writel(he_dev, 0x007f, G7_INMQ_S);
1395 he_writel(he_dev, 0x207f, G7_INMQ_L);
1397 he_writel(he_dev, 0x0000, G0_INMQ_S);
1398 he_writel(he_dev, 0x0008, G0_INMQ_L);
1400 he_writel(he_dev, 0x0001, G1_INMQ_S);
1401 he_writel(he_dev, 0x0009, G1_INMQ_L);
1403 he_writel(he_dev, 0x0002, G2_INMQ_S);
1404 he_writel(he_dev, 0x000a, G2_INMQ_L);
1406 he_writel(he_dev, 0x0003, G3_INMQ_S);
1407 he_writel(he_dev, 0x000b, G3_INMQ_L);
1409 he_writel(he_dev, 0x0004, G4_INMQ_S);
1410 he_writel(he_dev, 0x000c, G4_INMQ_L);
1412 he_writel(he_dev, 0x0005, G5_INMQ_S);
1413 he_writel(he_dev, 0x000d, G5_INMQ_L);
1415 he_writel(he_dev, 0x0006, G6_INMQ_S);
1416 he_writel(he_dev, 0x000e, G6_INMQ_L);
1418 he_writel(he_dev, 0x0007, G7_INMQ_S);
1419 he_writel(he_dev, 0x000f, G7_INMQ_L);
1424 he_writel(he_dev, 0x0, MCC);
1425 he_writel(he_dev, 0x0, OEC);
1426 he_writel(he_dev, 0x0, DCC);
1427 he_writel(he_dev, 0x0, CEC);
1431 he_init_cs_block(he_dev);
1435 if (he_init_cs_block_rcm(he_dev) < 0)
1440 he_init_tpdrq(he_dev);
1442 he_dev->tpd_pool = pci_pool_create("tpd", he_dev->pci_dev,
1444 if (he_dev->tpd_pool == NULL) {
1449 INIT_LIST_HEAD(&he_dev->outstanding_tpds);
1451 if (he_init_group(he_dev, 0) != 0)
1455 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
1456 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
1457 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
1458 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1461 he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
1462 he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
1463 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1465 he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
1467 he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
1468 he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
1469 he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
1471 he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
1473 he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
1474 he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
1475 he_writel(he_dev, TBRQ_THRESH(0x1),
1477 he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
1482 he_dev->hsp = pci_alloc_consistent(he_dev->pci_dev,
1483 sizeof(struct he_hsp), &he_dev->hsp_phys);
1484 if (he_dev->hsp == NULL) {
1488 memset(he_dev->hsp, 0, sizeof(struct he_hsp));
1489 he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
1494 if (he_isMM(he_dev))
1495 suni_init(he_dev->atm_dev);
1496 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)
1497 he_dev->atm_dev->phy->start(he_dev->atm_dev);
1504 val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);
1506 he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);
1507 he_phy_put(he_dev->atm_dev, SUNI_TACP_IUCHP_CLP, SUNI_TACP_IUCHP);
1512 reg = he_readl_mbox(he_dev, CS_ERCTL0);
1514 he_writel_mbox(he_dev, reg, CS_ERCTL0);
1516 reg = he_readl(he_dev, RC_CONFIG);
1518 he_writel(he_dev, reg, RC_CONFIG);
1521 he_dev->cs_stper[i].inuse = 0;
1522 he_dev->cs_stper[i].pcr = -1;
1524 he_dev->total_bw = 0;
1529 he_dev->atm_dev->ci_range.vpi_bits = he_dev->vpibits;
1530 he_dev->atm_dev->ci_range.vci_bits = he_dev->vcibits;
1532 he_dev->irq_peak = 0;
1533 he_dev->rbrq_peak = 0;
1534 he_dev->rbpl_peak = 0;
1535 he_dev->tbrq_peak = 0;
1543 he_stop(struct he_dev *he_dev)
1550 pci_dev = he_dev->pci_dev;
1554 if (he_dev->membase) {
1559 tasklet_disable(&he_dev->tasklet);
1563 reg = he_readl_mbox(he_dev, CS_ERCTL0);
1565 he_writel_mbox(he_dev, reg, CS_ERCTL0);
1567 reg = he_readl(he_dev, RC_CONFIG);
1569 he_writel(he_dev, reg, RC_CONFIG);
1573 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->stop)
1574 he_dev->atm_dev->phy->stop(he_dev->atm_dev);
1577 if (he_dev->irq)
1578 free_irq(he_dev->irq, he_dev);
1580 if (he_dev->irq_base)
1581 pci_free_consistent(he_dev->pci_dev, (CONFIG_IRQ_SIZE+1)
1582 * sizeof(struct he_irq), he_dev->irq_base, he_dev->irq_phys);
1584 if (he_dev->hsp)
1585 pci_free_consistent(he_dev->pci_dev, sizeof(struct he_hsp),
1586 he_dev->hsp, he_dev->hsp_phys);
1588 if (he_dev->rbpl_base) {
1589 list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
1590 pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
1592 pci_free_consistent(he_dev->pci_dev, CONFIG_RBPL_SIZE
1593 * sizeof(struct he_rbp), he_dev->rbpl_base, he_dev->rbpl_phys);
1596 kfree(he_dev->rbpl_virt);
1597 kfree(he_dev->rbpl_table);
1599 if (he_dev->rbpl_pool)
1600 pci_pool_destroy(he_dev->rbpl_pool);
1602 if (he_dev->rbrq_base)
1603 pci_free_consistent(he_dev->pci_dev, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
1604 he_dev->rbrq_base, he_dev->rbrq_phys);
1606 if (he_dev->tbrq_base)
1607 pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
1608 he_dev->tbrq_base, he_dev->tbrq_phys);
1610 if (he_dev->tpdrq_base)
1611 pci_free_consistent(he_dev->pci_dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
1612 he_dev->tpdrq_base, he_dev->tpdrq_phys);
1614 if (he_dev->tpd_pool)
1615 pci_pool_destroy(he_dev->tpd_pool);
1617 if (he_dev->pci_dev) {
1618 pci_read_config_word(he_dev->pci_dev, PCI_COMMAND, &command);
1620 pci_write_config_word(he_dev->pci_dev, PCI_COMMAND, command);
1623 if (he_dev->membase)
1624 iounmap(he_dev->membase);
1628 __alloc_tpd(struct he_dev *he_dev)
1633 tpd = pci_pool_alloc(he_dev->tpd_pool, GFP_ATOMIC|GFP_DMA, &mapping);
1661 he_service_rbrq(struct he_dev *he_dev, int group)
1664 ((unsigned long)he_dev->rbrq_base |
1665 he_dev->hsp->group[group].rbrq_tail);
1676 while (he_dev->rbrq_head != rbrq_tail) {
1680 he_dev->rbrq_head, group,
1681 RBRQ_ADDR(he_dev->rbrq_head),
1682 RBRQ_BUFLEN(he_dev->rbrq_head),
1683 RBRQ_CID(he_dev->rbrq_head),
1684 RBRQ_CRC_ERR(he_dev->rbrq_head) ? " CRC_ERR" : "",
1685 RBRQ_LEN_ERR(he_dev->rbrq_head) ? " LEN_ERR" : "",
1686 RBRQ_END_PDU(he_dev->rbrq_head) ? " END_PDU" : "",
1687 RBRQ_AAL5_PROT(he_dev->rbrq_head) ? " AAL5_PROT" : "",
1688 RBRQ_CON_CLOSED(he_dev->rbrq_head) ? " CON_CLOSED" : "",
1689 RBRQ_HBUF_ERR(he_dev->rbrq_head) ? " HBUF_ERR" : "");
1691 i = RBRQ_ADDR(he_dev->rbrq_head) >> RBP_IDX_OFFSET;
1692 heb = he_dev->rbpl_virt[i];
1694 cid = RBRQ_CID(he_dev->rbrq_head);
1696 vcc = __find_vcc(he_dev, cid);
1701 if (!RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
1702 clear_bit(i, he_dev->rbpl_table);
1704 pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
1710 if (RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
1716 heb->len = RBRQ_BUFLEN(he_dev->rbrq_head) * 4;
1717 clear_bit(i, he_dev->rbpl_table);
1721 if (RBRQ_CON_CLOSED(he_dev->rbrq_head)) {
1728 if (!RBRQ_END_PDU(he_dev->rbrq_head))
1731 if (RBRQ_LEN_ERR(he_dev->rbrq_head)
1732 || RBRQ_CRC_ERR(he_dev->rbrq_head)) {
1734 RBRQ_CRC_ERR(he_dev->rbrq_head)
1736 RBRQ_LEN_ERR(he_dev->rbrq_head)
1787 spin_unlock(&he_dev->global_lock);
1789 spin_lock(&he_dev->global_lock);
1797 pci_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
1802 he_dev->rbrq_head = (struct he_rbrq *)
1803 ((unsigned long) he_dev->rbrq_base |
1804 RBRQ_MASK(++he_dev->rbrq_head));
1810 if (updated > he_dev->rbrq_peak)
1811 he_dev->rbrq_peak = updated;
1813 he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
1821 he_service_tbrq(struct he_dev *he_dev, int group)
1824 ((unsigned long)he_dev->tbrq_base |
1825 he_dev->hsp->group[group].tbrq_tail);
1832 while (he_dev->tbrq_head != tbrq_tail) {
1837 TBRQ_TPD(he_dev->tbrq_head),
1838 TBRQ_EOS(he_dev->tbrq_head) ? " EOS" : "",
1839 TBRQ_MULTIPLE(he_dev->tbrq_head) ? " MULTIPLE" : "");
1841 list_for_each_entry(__tpd, &he_dev->outstanding_tpds, entry) {
1842 if (TPD_ADDR(__tpd->status) == TBRQ_TPD(he_dev->tbrq_head)) {
1851 TBRQ_TPD(he_dev->tbrq_head));
1855 if (TBRQ_EOS(he_dev->tbrq_head)) {
1857 he_mkcid(he_dev, tpd->vcc->vpi, tpd->vcc->vci));
1866 pci_unmap_single(he_dev->pci_dev,
1875 if (tpd->skb) { /* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */
1884 pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
1885 he_dev->tbrq_head = (struct he_tbrq *)
1886 ((unsigned long) he_dev->tbrq_base |
1887 TBRQ_MASK(++he_dev->tbrq_head));
1891 if (updated > he_dev->tbrq_peak)
1892 he_dev->tbrq_peak = updated;
1894 he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
1900 he_service_rbpl(struct he_dev *he_dev, int group)
1909 rbpl_head = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
1910 RBPL_MASK(he_readl(he_dev, G0_RBPL_S)));
1913 new_tail = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
1914 RBPL_MASK(he_dev->rbpl_tail+1));
1920 i = find_next_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE, he_dev->rbpl_hint);
1922 i = find_first_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE);
1926 he_dev->rbpl_hint = i + 1;
1928 heb = pci_pool_alloc(he_dev->rbpl_pool, GFP_ATOMIC|GFP_DMA, &mapping);
1932 list_add(&heb->entry, &he_dev->rbpl_outstanding);
1933 he_dev->rbpl_virt[i] = heb;
1934 set_bit(i, he_dev->rbpl_table);
1938 he_dev->rbpl_tail = new_tail;
1943 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
1950 struct he_dev *he_dev = (struct he_dev *) data;
1955 spin_lock_irqsave(&he_dev->global_lock, flags);
1957 while (he_dev->irq_head != he_dev->irq_tail) {
1960 type = ITYPE_TYPE(he_dev->irq_head->isw);
1961 group = ITYPE_GROUP(he_dev->irq_head->isw);
1968 if (he_service_rbrq(he_dev, group))
1969 he_service_rbpl(he_dev, group);
1975 he_service_tbrq(he_dev, group);
1978 he_service_rbpl(he_dev, group);
1986 spin_unlock_irqrestore(&he_dev->global_lock, flags);
1987 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->interrupt)
1988 he_dev->atm_dev->phy->interrupt(he_dev->atm_dev);
1989 spin_lock_irqsave(&he_dev->global_lock, flags);
1998 hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR));
2005 HPRINTK("isw not updated 0x%x\n", he_dev->irq_head->isw);
2007 he_service_rbrq(he_dev, 0);
2008 he_service_rbpl(he_dev, 0);
2009 he_service_tbrq(he_dev, 0);
2012 hprintk("bad isw 0x%x?\n", he_dev->irq_head->isw);
2015 he_dev->irq_head->isw = ITYPE_INVALID;
2017 he_dev->irq_head = (struct he_irq *) NEXT_ENTRY(he_dev->irq_base, he_dev->irq_head, IRQ_MASK);
2021 if (updated > he_dev->irq_peak)
2022 he_dev->irq_peak = updated;
2024 he_writel(he_dev,
2027 IRQ_TAIL(he_dev->irq_tail), IRQ0_HEAD);
2028 (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata; flush posted writes */
2030 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2037 struct he_dev *he_dev = (struct he_dev * )dev_id;
2040 if (he_dev == NULL)
2043 spin_lock_irqsave(&he_dev->global_lock, flags);
2045 he_dev->irq_tail = (struct he_irq *) (((unsigned long)he_dev->irq_base) |
2046 (*he_dev->irq_tailoffset << 2));
2048 if (he_dev->irq_tail == he_dev->irq_head) {
2050 he_dev->irq_tail = (struct he_irq *) ((unsigned long)he_dev->irq_base |
2051 ((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));
2052 (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata */
2056 if (he_dev->irq_head == he_dev->irq_tail /* && !IRQ_PENDING */)
2060 if (he_dev->irq_head != he_dev->irq_tail) {
2062 tasklet_schedule(&he_dev->tasklet);
2063 he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */
2064 (void) he_readl(he_dev, INT_FIFO); /* flush posted writes */
2066 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2072 __enqueue_tpd(struct he_dev *he_dev, struct he_tpd *tpd, unsigned cid)
2077 tpd, cid, he_dev->tpdrq_tail);
2079 /* new_tail = he_dev->tpdrq_tail; */
2080 new_tail = (struct he_tpdrq *) ((unsigned long) he_dev->tpdrq_base |
2081 TPDRQ_MASK(he_dev->tpdrq_tail+1));
2090 if (new_tail == he_dev->tpdrq_head) {
2091 he_dev->tpdrq_head = (struct he_tpdrq *)
2092 (((unsigned long)he_dev->tpdrq_base) |
2093 TPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));
2095 if (new_tail == he_dev->tpdrq_head) {
2101 pci_unmap_single(he_dev->pci_dev,
2113 pci_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
2119 list_add_tail(&tpd->entry, &he_dev->outstanding_tpds);
2120 he_dev->tpdrq_tail->tpd = TPD_ADDR(tpd->status);
2121 he_dev->tpdrq_tail->cid = cid;
2124 he_dev->tpdrq_tail = new_tail;
2126 he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
2127 (void) he_readl(he_dev, TPDRQ_T); /* flush posted writes */
2134 struct he_dev *he_dev = HE_DEV(vcc->dev);
2148 cid = he_mkcid(he_dev, vpi, vci);
2170 pcr_goal = he_dev->atm_dev->link_rate;
2190 spin_lock_irqsave(&he_dev->global_lock, flags);
2191 tsr0 = he_readl_tsr0(he_dev, cid);
2192 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2212 if ((he_dev->total_bw + pcr_goal)
2213 > (he_dev->atm_dev->link_rate * 9 / 10))
2219 spin_lock_irqsave(&he_dev->global_lock, flags); /* also protects he_dev->cs_stper[] */
2223 if (he_dev->cs_stper[reg].inuse == 0 ||
2224 he_dev->cs_stper[reg].pcr == pcr_goal)
2229 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2233 he_dev->total_bw += pcr_goal;
2236 ++he_dev->cs_stper[reg].inuse;
2237 he_dev->cs_stper[reg].pcr = pcr_goal;
2239 clock = he_is622(he_dev) ? 66667000 : 50000000;
2245 he_writel_mbox(he_dev, rate_to_atmf(period/2),
2247 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2258 spin_lock_irqsave(&he_dev->global_lock, flags);
2260 he_writel_tsr0(he_dev, tsr0, cid);
2261 he_writel_tsr4(he_dev, tsr4 | 1, cid);
2262 he_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) |
2264 he_writel_tsr2(he_dev, TSR2_ACR(rate_to_atmf(pcr_goal)), cid);
2265 he_writel_tsr9(he_dev, TSR9_OPEN_CONN, cid);
2267 he_writel_tsr3(he_dev, 0x0, cid);
2268 he_writel_tsr5(he_dev, 0x0, cid);
2269 he_writel_tsr6(he_dev, 0x0, cid);
2270 he_writel_tsr7(he_dev, 0x0, cid);
2271 he_writel_tsr8(he_dev, 0x0, cid);
2272 he_writel_tsr10(he_dev, 0x0, cid);
2273 he_writel_tsr11(he_dev, 0x0, cid);
2274 he_writel_tsr12(he_dev, 0x0, cid);
2275 he_writel_tsr13(he_dev, 0x0, cid);
2276 he_writel_tsr14(he_dev, 0x0, cid);
2277 (void) he_readl_tsr0(he_dev, cid); /* flush posted writes */
2278 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2299 spin_lock_irqsave(&he_dev->global_lock, flags);
2301 rsr0 = he_readl_rsr0(he_dev, cid);
2303 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2320 he_writel_rsr4(he_dev, rsr4, cid);
2321 he_writel_rsr1(he_dev, rsr1, cid);
2324 he_writel_rsr0(he_dev,
2326 (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
2328 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2348 struct he_dev *he_dev = HE_DEV(vcc->dev);
2358 cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
2369 spin_lock_irqsave(&he_dev->global_lock, flags);
2370 while (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {
2378 he_writel_rsr0(he_dev, RSR0_CLOSE_CONN, cid);
2379 (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
2380 he_writel_mbox(he_dev, cid, RXCON_CLOSE);
2381 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2424 spin_lock_irqsave(&he_dev->global_lock, flags);
2425 he_writel_tsr4_upper(he_dev, TSR4_FLUSH_CONN, cid);
2430 he_writel_tsr1(he_dev,
2435 he_writel_tsr14_upper(he_dev, TSR14_DELETE, cid);
2438 (void) he_readl_tsr4(he_dev, cid); /* flush posted writes */
2440 tpd = __alloc_tpd(he_dev);
2452 __enqueue_tpd(he_dev, tpd, cid);
2453 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2460 spin_lock_irqsave(&he_dev->global_lock, flags);
2467 while (!((tsr4 = he_readl_tsr4(he_dev, cid)) & TSR4_SESSION_ENDED)) {
2472 while (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) {
2484 if (he_dev->cs_stper[reg].inuse == 0)
2487 --he_dev->cs_stper[reg].inuse;
2489 he_dev->total_bw -= he_dev->cs_stper[reg].pcr;
2491 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2505 struct he_dev *he_dev = HE_DEV(vcc->dev);
2506 unsigned cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
2538 spin_lock_irqsave(&he_dev->global_lock, flags);
2540 tpd = __alloc_tpd(he_dev);
2547 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2567 tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev, skb->data,
2581 __enqueue_tpd(he_dev, tpd, cid);
2582 tpd = __alloc_tpd(he_dev);
2589 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2596 tpd->iovec[slot].addr = pci_map_single(he_dev->pci_dev,
2606 tpd->address0 = pci_map_single(he_dev->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2616 __enqueue_tpd(he_dev, tpd, cid);
2617 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2628 struct he_dev *he_dev = HE_DEV(atm_dev);
2641 spin_lock_irqsave(&he_dev->global_lock, flags);
2649 reg.val = he_readl(he_dev, reg.addr);
2653 he_readl_rcm(he_dev, reg.addr);
2657 he_readl_tcm(he_dev, reg.addr);
2661 he_readl_mbox(he_dev, reg.addr);
2667 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2690 struct he_dev *he_dev = HE_DEV(atm_dev);
2694 spin_lock_irqsave(&he_dev->global_lock, flags);
2695 he_writel(he_dev, val, FRAMER + (addr*4));
2696 (void) he_readl(he_dev, FRAMER + (addr*4)); /* flush posted writes */
2697 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2705 struct he_dev *he_dev = HE_DEV(atm_dev);
2708 spin_lock_irqsave(&he_dev->global_lock, flags);
2709 reg = he_readl(he_dev, FRAMER + (addr*4));
2710 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2720 struct he_dev *he_dev = HE_DEV(dev);
2736 he_dev->prod_id, he_dev->media & 0x40 ? "SM" : "MM");
2741 spin_lock_irqsave(&he_dev->global_lock, flags);
2742 mcc += he_readl(he_dev, MCC);
2743 oec += he_readl(he_dev, OEC);
2744 dcc += he_readl(he_dev, DCC);
2745 cec += he_readl(he_dev, CEC);
2746 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2754 CONFIG_IRQ_SIZE, he_dev->irq_peak);
2762 CONFIG_RBRQ_SIZE, he_dev->rbrq_peak);
2766 CONFIG_TBRQ_SIZE, he_dev->tbrq_peak);
2770 rbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));
2771 rbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));
2789 he_dev->cs_stper[i].pcr,
2790 he_dev->cs_stper[i].inuse);
2794 he_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9);
2801 static u8 read_prom_byte(struct he_dev *he_dev, int addr)
2807 val = readl(he_dev->membase + HOST_CNTL);
2812 he_writel(he_dev, val, HOST_CNTL);
2816 he_writel(he_dev, val | readtab[i], HOST_CNTL);
2822 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2824 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2831 he_writel(he_dev, val, HOST_CNTL);
2835 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2837 tmp_read = he_readl(he_dev, HOST_CNTL);
2840 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2844 he_writel(he_dev, val | ID_CS, HOST_CNTL);