Lines Matching refs:hpriv
442 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
443 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
444 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
445 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
446 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
596 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
598 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
601 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
603 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
606 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
608 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
611 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
613 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
616 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
618 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
620 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
623 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
626 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
909 struct mv_host_priv *hpriv = host->private_data;
910 return hpriv->base;
971 struct mv_host_priv *hpriv,
1001 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1015 writelfl(mask, hpriv->main_irq_mask_addr);
1021 struct mv_host_priv *hpriv = host->private_data;
1024 old_mask = hpriv->main_irq_mask;
1027 hpriv->main_irq_mask = new_mask;
1028 mv_write_main_irq_mask(new_mask, hpriv);
1049 struct mv_host_priv *hpriv = ap->host->private_data;
1063 if (IS_GEN_IIE(hpriv))
1072 struct mv_host_priv *hpriv = host->private_data;
1073 void __iomem *mmio = hpriv->base, *hc_mmio;
1076 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1095 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1153 struct mv_host_priv *hpriv = ap->host->private_data;
1157 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1457 struct mv_host_priv *hpriv = ap->host->private_data;
1460 old = readl(hpriv->base + GPIO_PORT_CTL);
1466 writel(new, hpriv->base + GPIO_PORT_CTL);
1510 struct mv_host_priv *hpriv = host->private_data;
1514 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1516 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1525 struct mv_host_priv *hpriv = host->private_data;
1530 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1534 for (port = 0; port < hpriv->n_ports; port++) {
1542 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1552 struct mv_host_priv *hpriv = ap->host->private_data;
1560 if (IS_GEN_I(hpriv))
1563 else if (IS_GEN_II(hpriv)) {
1567 } else if (IS_GEN_IIE(hpriv)) {
1589 if (!IS_SOC(hpriv))
1592 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1596 if (IS_SOC(hpriv)) {
1614 struct mv_host_priv *hpriv = ap->host->private_data;
1619 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1623 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1632 if (tag == 0 || !IS_GEN_I(hpriv))
1633 dma_pool_free(hpriv->sg_tbl_pool,
1654 struct mv_host_priv *hpriv = ap->host->private_data;
1664 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1669 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1675 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1682 if (tag == 0 || !IS_GEN_I(hpriv)) {
1683 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
2330 struct mv_host_priv *hpriv = ap->host->private_data;
2331 if (IS_GEN_II(hpriv))
2562 struct mv_host_priv *hpriv = ap->host->private_data;
2577 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2597 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2634 if (IS_GEN_I(hpriv)) {
2728 struct mv_host_priv *hpriv = ap->host->private_data;
2744 if (IS_GEN_I(hpriv)) {
2806 struct mv_host_priv *hpriv = host->private_data;
2807 void __iomem *mmio = hpriv->base, *hc_mmio;
2814 for (port = 0; port < hpriv->n_ports; port++) {
2849 if ((port + p) >= hpriv->n_ports)
2871 struct mv_host_priv *hpriv = host->private_data;
2878 err_cause = readl(mmio + hpriv->irq_cause_offset);
2886 writelfl(0, mmio + hpriv->irq_cause_offset);
2927 struct mv_host_priv *hpriv = host->private_data;
2929 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
2936 mv_write_main_irq_mask(0, hpriv);
2938 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2939 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2945 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2946 handled = mv_pci_error(host, hpriv->base);
2953 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
2979 struct mv_host_priv *hpriv = link->ap->host->private_data;
2980 void __iomem *mmio = hpriv->base;
2993 struct mv_host_priv *hpriv = link->ap->host->private_data;
2994 void __iomem *mmio = hpriv->base;
3021 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3026 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3034 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3035 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3038 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3050 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3056 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3071 tmp |= hpriv->signal[port].pre;
3072 tmp |= hpriv->signal[port].amps;
3079 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3084 mv_reset_channel(hpriv, mmio, port);
3103 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3121 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3128 mv5_reset_hc_port(hpriv, mmio,
3131 mv5_reset_one_hc(hpriv, mmio, hc);
3141 struct mv_host_priv *hpriv = host->private_data;
3152 ZERO(hpriv->irq_cause_offset);
3153 ZERO(hpriv->irq_mask_offset);
3161 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3165 mv5_reset_flash(hpriv, mmio);
3182 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3237 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3245 hpriv->signal[idx].amps = 0x7 << 8;
3246 hpriv->signal[idx].pre = 0x1 << 5;
3253 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3254 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3257 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3262 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3267 u32 hp_flags = hpriv->hp_flags;
3297 if (IS_SOC(hpriv))
3302 if (IS_GEN_IIE(hpriv))
3314 m2 |= hpriv->signal[port].amps;
3315 m2 |= hpriv->signal[port].pre;
3319 if (IS_GEN_IIE(hpriv)) {
3329 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3335 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3344 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3345 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3350 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3355 mv_reset_channel(hpriv, mmio, port);
3375 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3388 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3393 for (port = 0; port < hpriv->n_ports; port++)
3394 mv_soc_reset_hc_port(hpriv, mmio, port);
3396 mv_soc_reset_one_hc(hpriv, mmio);
3401 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3412 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3450 static bool soc_is_65n(struct mv_host_priv *hpriv)
3452 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3469 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3482 if (!IS_GEN_I(hpriv)) {
3495 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3497 if (IS_GEN_I(hpriv))
3533 struct mv_host_priv *hpriv = ap->host->private_data;
3535 void __iomem *mmio = hpriv->base;
3540 mv_reset_channel(hpriv, mmio, ap->port_no);
3555 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3576 struct mv_host_priv *hpriv = ap->host->private_data;
3579 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3640 struct mv_host_priv *hpriv = host->private_data;
3641 void __iomem *mmio = hpriv->base;
3644 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3654 struct mv_host_priv *hpriv = host->private_data;
3655 void __iomem *mmio = hpriv->base;
3668 struct mv_host_priv *hpriv = host->private_data;
3669 void __iomem *mmio = hpriv->base;
3680 struct mv_host_priv *hpriv = host->private_data;
3681 u32 hp_flags = hpriv->hp_flags;
3685 hpriv->ops = &mv5xxx_ops;
3705 hpriv->ops = &mv5xxx_ops;
3725 hpriv->ops = &mv6xxx_ops;
3777 hpriv->ops = &mv6xxx_ops;
3794 if (soc_is_65n(hpriv))
3795 hpriv->ops = &mv_soc_65n_ops;
3797 hpriv->ops = &mv_soc_ops;
3808 hpriv->hp_flags = hp_flags;
3810 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3811 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3812 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3814 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3815 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3816 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3835 struct mv_host_priv *hpriv = host->private_data;
3836 void __iomem *mmio = hpriv->base;
3838 rc = mv_chip_id(host, hpriv->board_idx);
3842 if (IS_SOC(hpriv)) {
3843 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3844 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3846 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3847 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3851 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3859 if (hpriv->ops->read_preamp)
3860 hpriv->ops->read_preamp(hpriv, port, mmio);
3862 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3866 hpriv->ops->reset_flash(hpriv, mmio);
3867 hpriv->ops->reset_bus(host, mmio);
3868 hpriv->ops->enable_leds(hpriv, mmio);
3889 if (!IS_SOC(hpriv)) {
3891 writelfl(0, mmio + hpriv->irq_cause_offset);
3894 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3908 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3910 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3912 if (!hpriv->crqb_pool)
3915 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3917 if (!hpriv->crpb_pool)
3920 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3922 if (!hpriv->sg_tbl_pool)
3928 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3934 writel(0, hpriv->base + WINDOW_CTRL(i));
3935 writel(0, hpriv->base + WINDOW_BASE(i));
3944 hpriv->base + WINDOW_CTRL(i));
3945 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3964 struct mv_host_priv *hpriv;
3991 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3993 if (!host || !hpriv)
3995 host->private_data = hpriv;
3996 hpriv->n_ports = n_ports;
3997 hpriv->board_idx = chip_soc;
4000 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4002 hpriv->base -= SATAHC0_REG_BASE;
4005 hpriv->clk = clk_get(&pdev->dev, NULL);
4006 if (IS_ERR(hpriv->clk))
4009 clk_enable(hpriv->clk);
4016 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4018 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4035 if (!IS_ERR(hpriv->clk)) {
4036 clk_disable(hpriv->clk);
4037 clk_put(hpriv->clk);
4057 struct mv_host_priv *hpriv = host->private_data;
4062 if (!IS_ERR(hpriv->clk)) {
4063 clk_disable(hpriv->clk);
4064 clk_put(hpriv->clk);
4086 struct mv_host_priv *hpriv = host->private_data;
4093 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
4179 struct mv_host_priv *hpriv = host->private_data;
4191 if (IS_GEN_I(hpriv))
4193 else if (IS_GEN_II(hpriv))
4195 else if (IS_GEN_IIE(hpriv))
4203 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4221 struct mv_host_priv *hpriv;
4231 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4232 if (!host || !hpriv)
4234 host->private_data = hpriv;
4235 hpriv->n_ports = n_ports;
4236 hpriv->board_idx = board_idx;
4249 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4255 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4261 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4262 unsigned int offset = port_mmio - hpriv->base;
4275 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4283 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);