Lines Matching refs:intercept
105 u64 intercept;
140 bool always; /* True if intercept is always on */
751 control->intercept = (1ULL << INTERCEPT_INTR) |
824 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
840 control->intercept |= (1ULL << INTERCEPT_PAUSE);
1015 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
1020 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1201 * But the L1 hypervisor may intercept selective cr0 writes.
1206 /* Remove bits that would trigger a real cr0 write intercept */
1510 * On an #MC intercept the MCE handler is not called automatically in
1530 * VMCB is undefined after a SHUTDOWN intercept
1644 if (svm->nested.intercept & 1ULL) {
1665 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1707 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1726 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1826 if (svm->nested.intercept & exit_bits)
1856 dst->intercept = from->intercept;
1934 * below only happens on a VMRUN instruction intercept which has
1999 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2046 nested_vmcb->control.intercept);
2123 svm->nested.intercept = nested_vmcb->control.intercept;
2133 /* We only want the cr8 intercept bits of the guest */
2139 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2156 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2395 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2767 pr_err("intercepts: %016llx\n", control->intercept);
2941 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3008 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
3011 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
3039 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3040 * get that intercept, this function will be called again though and
3041 * we'll get the vintr intercept.