Lines Matching refs:counter
68 /* returns the bit offset of the performance counter register */
112 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
114 BUG_ON(counter > NMI_MAX_COUNTER_BITS);
116 return !test_bit(counter, perfctr_nmi_owner);
122 unsigned int counter;
124 counter = nmi_perfctr_msr_to_bit(msr);
126 if (counter > NMI_MAX_COUNTER_BITS)
129 if (!test_and_set_bit(counter, perfctr_nmi_owner))
137 unsigned int counter;
139 counter = nmi_perfctr_msr_to_bit(msr);
141 if (counter > NMI_MAX_COUNTER_BITS)
144 clear_bit(counter, perfctr_nmi_owner);
150 unsigned int counter;
152 counter = nmi_evntsel_msr_to_bit(msr);
154 if (counter > NMI_MAX_COUNTER_BITS)
157 if (!test_and_set_bit(counter, evntsel_nmi_owner))
165 unsigned int counter;
167 counter = nmi_evntsel_msr_to_bit(msr);
169 if (counter > NMI_MAX_COUNTER_BITS)
172 clear_bit(counter, evntsel_nmi_owner);
221 * On Intel CPUs with P6/ARCH_PERFMON only 32 bits in the counter
223 * So, we can only program the counter with 31 bit values and
406 /* P6/ARCH_PERFMON has 32 bit counter write */
504 * still have other performance counter registers set to