Lines Matching defs:hwc
569 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
571 int idx = hwc->idx - X86_PMC_IDX_FIXED;
576 rdmsrl(hwc->config_base, ctrl_val);
578 wrmsrl(hwc->config_base, ctrl_val);
583 struct hw_perf_event *hwc = &event->hw;
585 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
591 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
592 intel_pmu_disable_fixed(hwc);
602 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
604 int idx = hwc->idx - X86_PMC_IDX_FIXED;
613 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
615 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
621 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
627 rdmsrl(hwc->config_base, ctrl_val);
630 wrmsrl(hwc->config_base, ctrl_val);
635 struct hw_perf_event *hwc = &event->hw;
637 if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
641 intel_pmu_enable_bts(hwc->config);
645 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
646 intel_pmu_enable_fixed(hwc);
653 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
770 struct hw_perf_event *hwc = &event->hw;
773 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
776 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))