Lines Matching defs:hwc
273 struct hw_perf_event *hwc = &event->hw;
276 int idx = hwc->idx;
290 prev_raw_count = local64_read(&hwc->prev_count);
291 rdmsrl(hwc->event_base + idx, new_raw_count);
293 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
309 local64_sub(delta, &hwc->period_left);
392 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
419 hwc->config |= val;
427 struct hw_perf_event *hwc = &event->hw;
430 if (!hwc->sample_period) {
431 hwc->sample_period = x86_pmu.max_period;
432 hwc->last_period = hwc->sample_period;
433 local64_set(&hwc->period_left, hwc->sample_period);
449 return set_ext_hw_attr(hwc, attr);
469 (hwc->sample_period == 1)) {
479 hwc->config |= config;
624 struct hw_perf_event *hwc;
637 hwc = &cpuc->event_list[i]->hw;
641 if (hwc->idx == -1)
645 if (!test_bit(hwc->idx, c->idxmsk))
649 if (test_bit(hwc->idx, used_mask))
652 __set_bit(hwc->idx, used_mask);
654 assign[i] = hwc->idx;
688 hwc = &cpuc->event_list[i]->hw;
762 struct hw_perf_event *hwc = &event->hw;
764 hwc->idx = cpuc->assign[i];
765 hwc->last_cpu = smp_processor_id();
766 hwc->last_tag = ++cpuc->tags[i];
768 if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
769 hwc->config_base = 0;
770 hwc->event_base = 0;
771 } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
772 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
777 hwc->event_base =
780 hwc->config_base = x86_pmu.eventsel;
781 hwc->event_base = x86_pmu.perfctr;
785 static inline int match_prev_assignment(struct hw_perf_event *hwc,
789 return hwc->idx == cpuc->assign[i] &&
790 hwc->last_cpu == smp_processor_id() &&
791 hwc->last_tag == cpuc->tags[i];
801 struct hw_perf_event *hwc;
821 hwc = &event->hw;
829 if (hwc->idx == -1 ||
830 match_prev_assignment(hwc, cpuc, i))
838 hwc = &event->hw;
840 if (!match_prev_assignment(hwc, cpuc, i))
857 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
860 wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
865 struct hw_perf_event *hwc = &event->hw;
867 wrmsrl(hwc->config_base + hwc->idx, hwc->config);
873 * Set the next IRQ period, based on the hwc->period_left value.
879 struct hw_perf_event *hwc = &event->hw;
880 s64 left = local64_read(&hwc->period_left);
881 s64 period = hwc->sample_period;
882 int ret = 0, idx = hwc->idx;
892 local64_set(&hwc->period_left, left);
893 hwc->last_period = period;
899 local64_set(&hwc->period_left, left);
900 hwc->last_period = period;
918 local64_set(&hwc->prev_count, (u64)-left);
920 wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
928 wrmsrl(hwc->event_base + idx,
957 struct hw_perf_event *hwc;
961 hwc = &event->hw;
1074 struct hw_perf_event *hwc = &event->hw;
1075 int idx = hwc->idx;
1127 struct hw_perf_event *hwc;
1148 hwc = &event->hw;