Lines Matching refs:address
55 u32 address;
102 rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
124 wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
131 u32 low = 0, high = 0, address = 0;
139 address = MSR_IA32_MC0_MISC + bank * 4;
141 address = (low & MASK_BLKPTR_LO) >> 21;
142 if (!address)
145 address += MCG_XBLK_ADDR;
147 ++address;
149 if (rdmsr_safe(address, &low, &high))
170 wrmsr(address, low, high);
172 threshold_defaults.address = address;
194 u32 low = 0, high = 0, address = 0;
206 address = MSR_IA32_MC0_MISC + bank * 4;
208 address = (low & MASK_BLKPTR_LO) >> 21;
209 if (!address)
211 address += MCG_XBLK_ADDR;
213 ++address;
216 if (rdmsr_safe(address, &low, &high))
238 rdmsrl(address, m.misc);
324 rdmsr(b->address, low, high);
402 u32 address)
411 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
432 b->address = address;
452 address = (low & MASK_BLKPTR_LO) >> 21;
453 if (!address)
455 address += MCG_XBLK_ADDR;
457 ++address;
460 err = allocate_threshold_blocks(cpu, bank, ++block, address);