Lines Matching defs:trigger
881 * trigger depending on the ELCR value. If an interrupt is listed as
882 * EISA conforming in the MP table, that means its trigger type must
945 int trigger;
948 * Determine IRQ trigger mode (edge or level sensitive):
954 trigger = default_ISA_trigger(idx);
956 trigger = default_PCI_trigger(idx);
966 trigger = default_EISA_trigger(idx);
976 trigger = default_MCA_trigger(idx);
982 trigger = 1;
990 trigger = 0;
996 trigger = 1;
1001 trigger = 1;
1007 trigger = 0;
1011 return trigger;
1330 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1333 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1334 trigger == IOAPIC_LEVEL)
1341 if (trigger)
1351 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1352 trigger == IOAPIC_LEVEL)
1363 unsigned int destination, int trigger,
1391 * actual level or edge trigger will be setup in the IO-APIC
1424 entry->trigger = trigger;
1430 if (trigger)
1436 int trigger, int polarity)
1464 irq, trigger, polarity);
1468 dest, trigger, polarity, cfg->vector, pin)) {
1475 ioapic_register_intr(irq, desc, trigger);
1621 entry.trigger = 0;
1722 entry.trigger,
2035 entry.trigger = 0; /* Edge */
2565 * Otherwise, we simulate the EOI message manually by changing the trigger
2848 entry1.trigger = 0;
2957 /* for edge trigger, setup_IO_APIC_irq already
2959 * so only need to unmask if it is level-trigger
2960 * do we really have level trigger timer?
3854 int trigger, polarity;
3875 trigger = irq_attr->trigger;
3890 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
4027 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
4046 *trigger = irq_trigger(idx);