Lines Matching refs:__u8
41 __u8 last_irr; /* edge detection */
42 __u8 irr; /* interrupt request register */
43 __u8 imr; /* interrupt mask register */
44 __u8 isr; /* interrupt service register */
45 __u8 priority_add; /* highest irq priority */
46 __u8 irq_base;
47 __u8 read_reg_select;
48 __u8 poll;
49 __u8 special_mask;
50 __u8 init_state;
51 __u8 auto_eoi;
52 __u8 rotate_on_auto_eoi;
53 __u8 special_fully_nested_mode;
54 __u8 init4; /* true if 4 byte init */
55 __u8 elcr; /* PIIX edge/trigger selection */
56 __u8 elcr_mask;
69 __u8 vector;
70 __u8 delivery_mode:3;
71 __u8 dest_mode:1;
72 __u8 delivery_status:1;
73 __u8 polarity:1;
74 __u8 remote_irr:1;
75 __u8 trig_mode:1;
76 __u8 mask:1;
77 __u8 reserve:7;
78 __u8 reserved[4];
79 __u8 dest_id;
109 __u8 type;
110 __u8 present, dpl, db, s, l, g, avl;
111 __u8 unusable;
112 __u8 padding;
136 __u8 fpr[8][16];
139 __u8 ftwx; /* in fxsave format */
140 __u8 pad1;
144 __u8 xmm[16][16];
212 __u8 count_latched;
213 __u8 status_latched;
214 __u8 status;
215 __u8 read_state;
216 __u8 write_state;
217 __u8 write_latch;
218 __u8 rw_mode;
219 __u8 mode;
220 __u8 bcd;
221 __u8 gate;
256 __u8 pit_reinject;
257 __u8 reserved[31];
272 __u8 injected;
273 __u8 nr;
274 __u8 has_error_code;
275 __u8 pad;
279 __u8 injected;
280 __u8 nr;
281 __u8 soft;
282 __u8 shadow;
285 __u8 injected;
286 __u8 pending;
287 __u8 masked;
288 __u8 pad;