Lines Matching refs:access
306 /** Hypervisor tile location for a memory access
644 * @param access PTE providing info on how to read the page table. This
647 * may be using to access the page table.
653 int hv_install_context(HV_PhysAddr page_table, HV_PTE access, HV_ASID asid,
669 /** PTE which defines access method for top of page table */
670 HV_PTE access;
1043 * INT_DMATLB_ACCESS_DWNCL (DMA TLB access violation)
1058 /** DMA TLB access violation downcall interrupt vector */
1135 * @param access The PTE describing how to read the memory
1138 unsigned long long hv_physaddr_read64(HV_PhysAddr addr, HV_PTE access);
1145 * @param access The PTE that says how to write the memory
1148 void hv_physaddr_write64(HV_PhysAddr addr, HV_PTE access,
1281 * sender has access, must not be the sending tile itself, and must have
1327 * number of tiles to which the sender has access; if not, the routine
1399 * access.
1454 * @param offset Driver-dependent offset. For a random-access device, this is
1497 * @param offset Driver-dependent offset. For a random-access device, this is
1632 * @param offset Driver-dependent offset. For a random-access device, this is
1678 * @param offset Driver-dependent offset. For a random-access device, this is
1832 /** Data is not resident in any caches; loads and stores access memory
1941 * access the virtual addresses mapped by this PTE. Otherwise, only