Lines Matching refs:REG1
98 #define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
99 661: casa [TSB] ASI_N, REG1, REG2; \
102 casa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
105 #define TSB_CAS_TAG(TSB, REG1, REG2) \
106 661: casxa [TSB] ASI_N, REG1, REG2; \
109 casxa [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
119 #define TSB_LOCK_TAG(TSB, REG1, REG2) \
120 99: TSB_LOAD_TAG_HIGH(TSB, REG1); \
122 andcc REG1, REG2, %g0; \
125 TSB_CAS_TAG_HIGH(TSB, REG1, REG2); \
126 cmp REG1, REG2; \
142 #define KTSB_LOCK_TAG(TSB, REG1, REG2) \
143 99: lduwa [TSB] ASI_N, REG1; \
145 andcc REG1, REG2, %g0; \
148 casa [TSB] ASI_N, REG1, REG2;\
149 cmp REG1, REG2; \
160 * REG1. Jumps to FAIL_LABEL on early page table walk termination.
163 #define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL) \
164 sethi %hi(swapper_pg_dir), REG1; \
165 or REG1, %lo(swapper_pg_dir), REG1; \
169 lduw [REG1 + REG2], REG1; \
170 brz,pn REG1, FAIL_LABEL; \
173 sllx REG1, 11, REG1; \
175 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
176 brz,pn REG1, FAIL_LABEL; \
179 sllx REG1, 11, REG1; \
181 add REG1, REG2, REG1;
184 * pointer in REG1. Jumps to FAIL_LABEL on early page table walk
188 * VADDR will not be clobbered, but REG1 and REG2 will.
190 #define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL) \
194 lduwa [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
195 brz,pn REG1, FAIL_LABEL; \
198 sllx REG1, 11, REG1; \
200 lduwa [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
201 brz,pn REG1, FAIL_LABEL; \
204 sllx REG1, 11, REG1; \
206 add REG1, REG2, REG1;
210 * the resulting PTE value will be left in REG1. VADDR is preserved
213 #define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
214 sethi %hi(prom_trans), REG1; \
215 or REG1, %lo(prom_trans), REG1; \
216 97: ldx [REG1 + 0x00], REG2; \
219 ldx [REG1 + 0x08], REG3; \
225 ldx [REG1 + 0x10], REG3; \
228 add REG3, REG2, REG1; \
230 add REG1, (3 * 8), REG1; \
243 * on TSB hit. REG1, REG2, REG3, and REG4 are used as temporaries
244 * and the found TTE will be left in REG1. REG3 and REG4 must
249 #define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
250 sethi %hi(swapper_tsb), REG1; \
251 or REG1, %lo(swapper_tsb), REG1; \
255 add REG1, REG2, REG2; \
259 mov REG4, REG1;
265 #define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
266 sethi %hi(swapper_4m_tsb), REG1; \
267 or REG1, %lo(swapper_4m_tsb), REG1; \
270 add REG1, REG2, REG2; \
274 mov REG4, REG1;