Lines Matching refs:SR
22 * SR fields.
83 getcon SR, r6; \
85 putcon r6, SR;
88 getcon SR, r6; \
90 putcon r6, SR;
606 ! construct useful SR for handle_exception
613 ! SSR is now the current SR with the MD and MMU bits set
818 /* We are in a safe position to turn SR.BL off, but set IMASK=0xf
831 getcon SR, r6
834 putcon r6, SR
837 putcon r6, SR
909 getcon SR, r7
1039 getcon SR, r59
1042 putcon r59, SR /* SR.BL = 1, keep nesting out */
1314 shlli r2, 16, r2 /* align new ASID against SR.ASID */
1315 andc r0, r4, r0 /* efface old ASID from SR */
1365 getcon sr, r0 /* r0 = saved original SR */
1414 getcon sr, r0 /* r0 = saved original SR */
2059 /* Now that exception vectors are set up reset SR.BL */
2060 getcon SR, r22
2063 putcon r22, SR