Lines Matching refs:CLKDEV_CON_ID
128 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
132 CLKDEV_CON_ID("extal", &extal_clk),
133 CLKDEV_CON_ID("pll_clk", &pll_clk),
136 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
137 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
138 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
139 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
140 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
141 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
175 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
176 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
177 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
178 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
179 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
180 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
181 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
182 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
244 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
245 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
246 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
247 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
248 CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
249 CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
250 CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
251 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
252 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
253 CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
254 CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),