Lines Matching refs:CLKDEV_CON_ID
119 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
123 CLKDEV_CON_ID("extal", &extal_clk),
124 CLKDEV_CON_ID("pll_clk", &pll_clk),
127 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
128 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
129 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
130 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
132 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
133 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
134 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
168 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
169 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
170 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
171 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
172 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
173 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
205 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
206 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
207 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
208 CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
209 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
210 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
211 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),