Lines Matching refs:CLKDEV_CON_ID
178 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
182 CLKDEV_CON_ID("rclk", &r_clk),
183 CLKDEV_CON_ID("extal", &extal_clk),
184 CLKDEV_CON_ID("dll_clk", &dll_clk),
185 CLKDEV_CON_ID("pll_clk", &pll_clk),
188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
190 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
191 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
192 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
193 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
194 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
195 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
196 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
202 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
203 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
220 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
221 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
222 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
239 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
240 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
241 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
242 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
243 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
244 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
245 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
246 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
247 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
248 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
249 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
250 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
251 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
252 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),