Lines Matching refs:PA_FPGA
36 #define PA_FPGA (PA_PERIPHERAL + 0x01000000)
41 #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */
42 #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */
43 #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */
44 #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */
45 #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */
46 #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */
47 #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */
48 #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */
49 #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */
50 #define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */
51 #define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */
52 #define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */
54 #define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */
55 #define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */
56 #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */
57 #define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */
58 #define FPGA_EASR (PA_FPGA + 0x110) /* External area select */
59 #define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */
60 #define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */
61 #define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */
62 #define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */
63 #define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */
64 #define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */
65 #define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */