Lines Matching defs:HD64461_IO_OFFSET
17 #define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
18 #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
24 #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
29 #define HD64461_STBCR HD64461_IO_OFFSET(0x00000000)
46 #define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
49 #define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
52 #define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
55 #define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
58 #define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
69 #define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
74 #define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
75 #define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
76 #define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
77 #define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
78 #define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
79 #define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
82 #define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
85 #define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
86 #define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
87 #define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
88 #define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
90 #define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
91 #define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
92 #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
102 #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
103 #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
104 #define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
105 #define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
106 #define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
107 #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
108 #define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
111 #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
112 #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
113 #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
114 #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
115 #define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
116 #define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
117 #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
118 #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
119 #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
120 #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
121 #define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
122 #define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
126 #define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
127 #define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
128 #define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
129 #define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
130 #define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
132 #define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
133 #define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
134 #define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
135 #define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
136 #define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
194 #define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
197 #define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
200 #define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
203 #define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
204 #define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
205 #define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
206 #define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
209 #define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
210 #define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
211 #define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
212 #define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
215 #define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
216 #define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
217 #define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
218 #define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
221 #define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
222 #define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
223 #define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
224 #define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
227 #define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
228 #define HD64461_NIMR HD64461_IO_OFFSET(0x5002)