Lines Matching refs:hose
90 struct pci_channel *hose = dev_id;
96 addr = __raw_readl(hose->reg_base + SH4_PCIALR);
101 status = __raw_readw(hose->reg_base + PCI_STATUS);
107 cmd = pcibios_handle_status_errors(addr, status, hose);
109 __raw_writew(cmd, hose->reg_base + PCI_STATUS);
115 status = __raw_readl(hose->reg_base + SH4_PCIAINT);
123 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
128 status = __raw_readl(hose->reg_base + SH4_PCIINT);
136 __raw_writel(cmd, hose->reg_base + SH4_PCIINT);
143 struct pci_channel *hose = dev_id;
150 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
154 hose->serr_timer.expires = jiffies + HZ;
155 add_timer(&hose->serr_timer);
160 static int __init sh7780_pci_setup_irqs(struct pci_channel *hose)
165 __raw_writel(0, hose->reg_base + SH4_PCIAINT);
173 PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);
175 ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, IRQF_DISABLED,
176 "PCI SERR interrupt", hose);
188 ret = request_irq(hose->err_irq, sh7780_pci_err_irq, IRQF_SHARED,
189 "PCI ERR interrupt", hose);
191 free_irq(hose->serr_irq, hose);
198 SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);
206 SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);
211 static inline void __init sh7780_pci_teardown_irqs(struct pci_channel *hose)
213 free_irq(hose->err_irq, hose);
214 free_irq(hose->serr_irq, hose);
217 static void __init sh7780_pci66_init(struct pci_channel *hose)
221 if (!pci_is_66mhz_capable(hose, 0, 0))
225 tmp = __raw_readl(hose->reg_base + SH4_PCICR);
227 __raw_writel(tmp, hose->reg_base + SH4_PCICR);
230 tmp = __raw_readw(hose->reg_base + PCI_STATUS);
232 __raw_writew(tmp, hose->reg_base + PCI_STATUS);
235 tmp = __raw_readl(hose->reg_base + SH4_PCICR);
237 __raw_writel(tmp, hose->reg_base + SH4_PCICR);