Lines Matching refs:so
63 struct sh_mobile_lcdc_sys_bus_ops *so)
65 return so->read_data(sohandle);
69 struct sh_mobile_lcdc_sys_bus_ops *so,
73 so->write_data(sohandle, v); /* PTH4/LCDRS High [param, 17:0] */
75 so->write_index(sohandle, v); /* PTH4/LCDRS Low [cmd, 7:0] */
79 struct sh_mobile_lcdc_sys_bus_ops *so,
85 write_reg(sohandle, so, 1, data[i]);
89 struct sh_mobile_lcdc_sys_bus_ops *so)
94 write_reg(sohandle, so, 0, 0xb0);
95 write_reg(sohandle, so, 1, 0x00);
98 write_reg(sohandle, so, 0, 0xb1);
99 write_reg(sohandle, so, 1, 0x00);
102 write_reg(sohandle, so, 0, 0xbf);
106 read_reg(sohandle, so);
109 device_code = ((read_reg(sohandle, so) & 0xff) << 24);
110 device_code |= ((read_reg(sohandle, so) & 0xff) << 16);
111 device_code |= ((read_reg(sohandle, so) & 0xff) << 8);
112 device_code |= (read_reg(sohandle, so) & 0xff);
118 struct sh_mobile_lcdc_sys_bus_ops *so)
120 write_reg(sohandle, so, 0, 0x2c);
124 struct sh_mobile_lcdc_sys_bus_ops *so)
129 write_memory_start(sohandle, so);
133 write_reg(sohandle, so, 1, 0x00);
137 struct sh_mobile_lcdc_sys_bus_ops *so)
140 write_reg(sohandle, so, 0, 0xb0);
141 write_reg(sohandle, so, 1, 0x00);
144 write_reg(sohandle, so, 0, 0xb1);
145 write_reg(sohandle, so, 1, 0x00);
148 write_reg(sohandle, so, 0, 0xb3);
149 write_data(sohandle, so, data_frame_if, ARRAY_SIZE(data_frame_if));
152 write_reg(sohandle, so, 0, 0xb4);
153 write_reg(sohandle, so, 1, 0x00); /* DBI, internal clock */
156 write_reg(sohandle, so, 0, 0xc0);
157 write_data(sohandle, so, data_panel, ARRAY_SIZE(data_panel));
160 write_reg(sohandle, so, 0, 0xc1);
161 write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
164 write_reg(sohandle, so, 0, 0xc2);
165 write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
168 write_reg(sohandle, so, 0, 0xc3);
169 write_data(sohandle, so, data_timing, ARRAY_SIZE(data_timing));
172 write_reg(sohandle, so, 0, 0xc4);
173 write_data(sohandle, so, data_timing_src, ARRAY_SIZE(data_timing_src));
176 write_reg(sohandle, so, 0, 0xc8);
177 write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
180 write_reg(sohandle, so, 0, 0xc9);
181 write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
184 write_reg(sohandle, so, 0, 0xca);
185 write_data(sohandle, so, data_gamma, ARRAY_SIZE(data_gamma));
188 write_reg(sohandle, so, 0, 0xd0);
189 write_data(sohandle, so, data_power, ARRAY_SIZE(data_power));
192 write_reg(sohandle, so, 0, 0xd1);
193 write_reg(sohandle, so, 1, 0x00);
194 write_reg(sohandle, so, 1, 0x0f);
195 write_reg(sohandle, so, 1, 0x02);
198 write_reg(sohandle, so, 0, 0xd2);
199 write_reg(sohandle, so, 1, 0x63);
200 write_reg(sohandle, so, 1, 0x24);
203 write_reg(sohandle, so, 0, 0xd3);
204 write_reg(sohandle, so, 1, 0x63);
205 write_reg(sohandle, so, 1, 0x24);
208 write_reg(sohandle, so, 0, 0xd4);
209 write_reg(sohandle, so, 1, 0x63);
210 write_reg(sohandle, so, 1, 0x24);
212 write_reg(sohandle, so, 0, 0xd8);
213 write_reg(sohandle, so, 1, 0x77);
214 write_reg(sohandle, so, 1, 0x77);
217 write_reg(sohandle, so, 0, 0x35);
218 write_reg(sohandle, so, 1, 0x00);
221 write_reg(sohandle, so, 0, 0x44);
222 write_reg(sohandle, so, 1, 0x00);
223 write_reg(sohandle, so, 1, 0x00);
226 write_reg(sohandle, so, 0, 0x2a);
227 write_reg(sohandle, so, 1, 0x00);
228 write_reg(sohandle, so, 1, 0x00);
229 write_reg(sohandle, so, 1, 0x00);
230 write_reg(sohandle, so, 1, 0xef);
233 write_reg(sohandle, so, 0, 0x2b);
234 write_reg(sohandle, so, 1, 0x00);
235 write_reg(sohandle, so, 1, 0x00);
236 write_reg(sohandle, so, 1, 0x01);
237 write_reg(sohandle, so, 1, 0x8f);
240 write_reg(sohandle, so, 0, 0x11);
245 clear_memory(sohandle, so);
248 write_reg(sohandle, so, 0, 0x29);
251 write_memory_start(sohandle, so);
255 struct sh_mobile_lcdc_sys_bus_ops *so)
267 if (read_device_code(sohandle, so) != 0x01221517)
272 display_on(sohandle, so);
277 struct sh_mobile_lcdc_sys_bus_ops *so)
279 write_memory_start(sohandle, so);