Lines Matching refs:PPCSPE
1910 #define PPCSPE PPC_OPCODE_SPE
2264 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2266 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2268 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2269 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2270 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2271 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2272 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2273 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2274 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2275 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2276 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2278 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2283 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2287 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2288 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2289 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2293 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2294 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2295 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2298 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2299 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2300 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2301 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2302 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2307 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2308 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2309 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2310 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2311 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2313 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2314 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2316 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2318 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2319 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2320 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2322 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2323 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2324 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2326 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2328 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2330 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2332 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2333 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2334 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2337 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2338 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2339 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2341 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2342 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2343 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2344 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2345 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2346 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2347 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2348 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2349 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2351 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2352 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2353 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2354 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2355 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2357 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2358 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2359 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2360 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2361 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2362 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2363 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2364 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2365 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2366 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2367 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2368 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2369 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2370 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2371 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2372 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2373 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2399 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2400 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2401 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2402 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2403 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2404 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2405 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2406 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2407 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2408 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2409 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2410 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2411 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2412 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2413 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2414 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2416 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2417 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2418 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2419 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2420 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2421 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2422 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2423 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2424 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2425 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2426 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2427 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2429 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2430 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2431 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2432 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2433 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2434 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2435 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2436 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2437 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2438 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2439 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2440 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2442 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2443 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2444 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2445 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2446 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2447 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2449 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2450 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2451 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2452 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2453 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2454 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2456 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2457 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2458 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2459 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2460 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2461 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2462 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2463 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2465 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2466 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2468 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2469 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2470 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2471 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2473 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2474 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2475 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2476 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2478 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2479 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2480 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2481 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2482 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2483 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2484 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2485 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2487 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2488 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2489 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2490 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2492 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2493 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2494 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2495 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2497 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2498 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2499 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2500 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2502 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2503 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2504 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2505 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2507 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2509 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2510 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
3871 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3874 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3875 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3876 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
4189 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4192 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
4193 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
4194 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },