Lines Matching refs:hose
50 static int __init fsl_pcie_check_link(struct pci_controller *hose)
54 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
98 static void __init setup_pci_atmu(struct pci_controller *hose,
108 char *name = hose->dn->full_name;
114 dev_err(hose->parent, "Unable to map ATMU registers\n");
126 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
129 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
130 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
132 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
133 hose->pci_mem_offset);
137 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
143 if (hose->io_resource.flags & IORESOURCE_IO) {
149 (u64)hose->io_resource.start,
150 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
151 (u64)hose->io_base_phys);
152 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
154 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
157 | (__ilog2(hose->io_resource.end
158 - hose->io_resource.start + 1) - 1));
163 paddr_hi -= hose->pci_mem_offset;
164 paddr_lo -= hose->pci_mem_offset;
177 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
178 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
186 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
198 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
215 hose->dma_window_base_cur = 0x00000000;
216 hose->dma_window_size = (resource_size_t)sz;
241 hose->dma_window_base_cur = 0x00000000;
242 hose->dma_window_size = (resource_size_t)paddr;
245 if (hose->dma_window_size < mem) {
259 (u64)hose->dma_window_size);
265 static void __init setup_pci_cmd(struct pci_controller *hose)
270 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
273 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
275 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
280 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
282 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
288 struct pci_controller *hose = pci_bus_to_host(bus);
291 if ((bus->parent == hose->bus) &&
293 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
294 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
316 struct pci_controller *hose;
335 hose = pcibios_alloc_controller(dev);
336 if (!hose)
339 hose->first_busno = bus_range ? bus_range[0] : 0x0;
340 hose->last_busno = bus_range ? bus_range[1] : 0xff;
342 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
344 setup_pci_cmd(hose);
347 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
348 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
350 if (fsl_pcie_check_link(hose))
351 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
356 (unsigned long long)rsrc.start, hose->first_busno,
357 hose->last_busno);
360 hose, hose->cfg_addr, hose->cfg_data);
364 pci_process_bridge_OF_ranges(hose, dev, is_primary);
367 setup_pci_atmu(hose, &rsrc);
443 struct pci_controller *hose = pci_bus_to_host(bus);
445 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
447 if (bus->number == hose->first_busno ||
448 bus->primary == hose->first_busno) {
454 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
464 struct pci_controller *hose = pci_bus_to_host(bus);
465 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
476 if (bus->number == hose->first_busno)
516 struct pci_controller *hose = pci_bus_to_host(bus);
524 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
547 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
573 WARN_ON(hose->dn->data);
574 hose->dn->data = pcie;
575 hose->ops = &mpc83xx_pcie_ops;
580 if (fsl_pcie_check_link(hose))
581 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
596 struct pci_controller *hose;
647 hose = pcibios_alloc_controller(dev);
648 if (!hose)
651 hose->first_busno = bus_range ? bus_range[0] : 0;
652 hose->last_busno = bus_range ? bus_range[1] : 0xff;
655 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
659 setup_indirect_pci(hose, rsrc_cfg.start,
665 (unsigned long long)rsrc_reg.start, hose->first_busno,
666 hose->last_busno);
669 hose, hose->cfg_addr, hose->cfg_data);
673 pci_process_bridge_OF_ranges(hose, dev, primary);
677 pcibios_free_controller(hose);