Lines Matching refs:priv2
176 struct spu_priv2 __iomem *priv2 = spu->priv2;
181 switch (in_be64(&priv2->mfc_control_RW) &
184 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
190 csa->priv2.mfc_control_RW =
191 in_be64(&priv2->mfc_control_RW) |
195 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
196 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
200 csa->priv2.mfc_control_RW =
201 in_be64(&priv2->mfc_control_RW) &
256 struct spu_priv2 __iomem *priv2 = spu->priv2;
266 csa->priv2.mfc_control_RW &= ~mask;
267 csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
272 struct spu_priv2 __iomem *priv2 = spu->priv2;
278 out_be64(&priv2->mfc_control_RW,
342 struct spu_priv2 __iomem *priv2 = spu->priv2;
349 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
351 csa->priv2.puq[i].mfc_cq_data0_RW =
352 in_be64(&priv2->puq[i].mfc_cq_data0_RW);
353 csa->priv2.puq[i].mfc_cq_data1_RW =
354 in_be64(&priv2->puq[i].mfc_cq_data1_RW);
355 csa->priv2.puq[i].mfc_cq_data2_RW =
356 in_be64(&priv2->puq[i].mfc_cq_data2_RW);
357 csa->priv2.puq[i].mfc_cq_data3_RW =
358 in_be64(&priv2->puq[i].mfc_cq_data3_RW);
361 csa->priv2.spuq[i].mfc_cq_data0_RW =
362 in_be64(&priv2->spuq[i].mfc_cq_data0_RW);
363 csa->priv2.spuq[i].mfc_cq_data1_RW =
364 in_be64(&priv2->spuq[i].mfc_cq_data1_RW);
365 csa->priv2.spuq[i].mfc_cq_data2_RW =
366 in_be64(&priv2->spuq[i].mfc_cq_data2_RW);
367 csa->priv2.spuq[i].mfc_cq_data3_RW =
368 in_be64(&priv2->spuq[i].mfc_cq_data3_RW);
410 struct spu_priv2 __iomem *priv2 = spu->priv2;
416 csa->priv2.spu_tag_status_query_RW =
417 in_be64(&priv2->spu_tag_status_query_RW);
422 struct spu_priv2 __iomem *priv2 = spu->priv2;
428 csa->priv2.spu_cmd_buf1_RW = in_be64(&priv2->spu_cmd_buf1_RW);
429 csa->priv2.spu_cmd_buf2_RW = in_be64(&priv2->spu_cmd_buf2_RW);
434 struct spu_priv2 __iomem *priv2 = spu->priv2;
440 csa->priv2.spu_atomic_status_RW = in_be64(&priv2->spu_atomic_status_RW);
465 struct spu_priv2 __iomem *priv2 = spu->priv2;
471 out_be64(&priv2->mfc_control_RW,
479 struct spu_priv2 __iomem *priv2 = spu->priv2;
485 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
520 struct spu_priv2 __iomem *priv2 = spu->priv2;
525 csa->priv2.spu_privcntl_RW = in_be64(&priv2->spu_privcntl_RW);
530 struct spu_priv2 __iomem *priv2 = spu->priv2;
536 out_be64(&priv2->spu_privcntl_RW, 0UL);
542 struct spu_priv2 __iomem *priv2 = spu->priv2;
547 csa->priv2.spu_lslr_RW = in_be64(&priv2->spu_lslr_RW);
552 struct spu_priv2 __iomem *priv2 = spu->priv2;
558 out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);
564 struct spu_priv2 __iomem *priv2 = spu->priv2;
569 csa->priv2.spu_cfg_RW = in_be64(&priv2->spu_cfg_RW);
614 struct spu_priv2 __iomem *priv2 = spu->priv2;
619 csa->priv2.puint_mb_R = in_be64(&priv2->puint_mb_R);
624 struct spu_priv2 __iomem *priv2 = spu->priv2;
632 out_be64(&priv2->spu_chnlcntptr_RW, 1);
633 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW);
638 out_be64(&priv2->spu_chnlcntptr_RW, idx);
640 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW);
641 csa->spu_chnlcnt_RW[idx] = in_be64(&priv2->spu_chnlcnt_RW);
642 out_be64(&priv2->spu_chnldata_RW, 0UL);
643 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
650 struct spu_priv2 __iomem *priv2 = spu->priv2;
656 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
658 csa->spu_chnlcnt_RW[29] = in_be64(&priv2->spu_chnlcnt_RW);
660 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW);
662 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
668 struct spu_priv2 __iomem *priv2 = spu->priv2;
673 out_be64(&priv2->spu_chnlcntptr_RW, 21UL);
675 csa->spu_chnlcnt_RW[21] = in_be64(&priv2->spu_chnlcnt_RW);
681 struct spu_priv2 __iomem *priv2 = spu->priv2;
692 out_be64(&priv2->spu_chnlcntptr_RW, idx);
694 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
701 struct spu_priv2 __iomem *priv2 = spu->priv2;
707 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
743 csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
971 struct spu_priv2 __iomem *priv2 = spu->priv2;
977 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
985 struct spu_priv2 __iomem *priv2 = spu->priv2;
991 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1074 struct spu_priv2 __iomem *priv2 = spu->priv2;
1083 out_be64(&priv2->spu_chnlcntptr_RW, 1);
1084 out_be64(&priv2->spu_chnldata_RW, 0UL);
1089 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1091 out_be64(&priv2->spu_chnldata_RW, 0UL);
1092 out_be64(&priv2->spu_chnlcnt_RW, 0UL);
1099 struct spu_priv2 __iomem *priv2 = spu->priv2;
1110 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1112 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1270 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1299 csa->lscsa->ppuint_mb.slot[0] = csa->priv2.puint_mb_R;
1319 struct spu_priv2 __iomem *priv2 = spu->priv2;
1324 out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);
1393 struct spu_priv2 __iomem *priv2 = spu->priv2;
1399 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
1425 struct spu_priv2 __iomem *priv2 = spu->priv2;
1432 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1434 out_be64(&priv2->puq[i].mfc_cq_data0_RW,
1435 csa->priv2.puq[i].mfc_cq_data0_RW);
1436 out_be64(&priv2->puq[i].mfc_cq_data1_RW,
1437 csa->priv2.puq[i].mfc_cq_data1_RW);
1438 out_be64(&priv2->puq[i].mfc_cq_data2_RW,
1439 csa->priv2.puq[i].mfc_cq_data2_RW);
1440 out_be64(&priv2->puq[i].mfc_cq_data3_RW,
1441 csa->priv2.puq[i].mfc_cq_data3_RW);
1444 out_be64(&priv2->spuq[i].mfc_cq_data0_RW,
1445 csa->priv2.spuq[i].mfc_cq_data0_RW);
1446 out_be64(&priv2->spuq[i].mfc_cq_data1_RW,
1447 csa->priv2.spuq[i].mfc_cq_data1_RW);
1448 out_be64(&priv2->spuq[i].mfc_cq_data2_RW,
1449 csa->priv2.spuq[i].mfc_cq_data2_RW);
1450 out_be64(&priv2->spuq[i].mfc_cq_data3_RW,
1451 csa->priv2.spuq[i].mfc_cq_data3_RW);
1481 struct spu_priv2 __iomem *priv2 = spu->priv2;
1486 out_be64(&priv2->spu_tag_status_query_RW,
1487 csa->priv2.spu_tag_status_query_RW);
1493 struct spu_priv2 __iomem *priv2 = spu->priv2;
1499 out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);
1500 out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);
1506 struct spu_priv2 __iomem *priv2 = spu->priv2;
1511 out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);
1566 struct spu_priv2 __iomem *priv2 = spu->priv2;
1575 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1577 out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);
1578 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);
1585 struct spu_priv2 __iomem *priv2 = spu->priv2;
1599 out_be64(&priv2->spu_chnlcntptr_RW, idx);
1601 out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);
1608 struct spu_priv2 __iomem *priv2 = spu->priv2;
1613 out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);
1619 struct spu_priv2 __iomem *priv2 = spu->priv2;
1624 out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);
1649 struct spu_priv2 __iomem *priv2 = spu->priv2;
1655 out_be64(&priv2->spu_chnlcntptr_RW, 29UL);
1657 out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);
1659 out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);
1681 struct spu_priv2 __iomem *priv2 = spu->priv2;
1689 dummy = in_be64(&priv2->puint_mb_R);
1736 struct spu_priv2 __iomem *priv2 = spu->priv2;
1741 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
1883 struct spu_priv2 __iomem *priv2 = spu->priv2;
1895 out_be64(&priv2->spu_privcntl_RW, 4LL);
1903 out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);
2174 csa->priv2.spu_lslr_RW = LS_ADDR_MASK;
2175 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |