Lines Matching refs:priv1
119 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
120 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
121 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
224 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
449 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
586 csa->priv1.resource_allocation_groupID_RW =
588 csa->priv1.resource_allocation_enable_RW =
1240 csa->priv1.resource_allocation_groupID_RW);
1242 csa->priv1.resource_allocation_enable_RW);
1519 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
1701 spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
1778 spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
1779 spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
1780 spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
2156 csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
2162 csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
2165 csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
2167 csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |