Lines Matching refs:mfc_control_RW
181 switch (in_be64(&priv2->mfc_control_RW) &
184 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
190 csa->priv2.mfc_control_RW =
191 in_be64(&priv2->mfc_control_RW) |
195 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
196 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
200 csa->priv2.mfc_control_RW =
201 in_be64(&priv2->mfc_control_RW) &
266 csa->priv2.mfc_control_RW &= ~mask;
267 csa->priv2.mfc_control_RW |= in_be64(&priv2->mfc_control_RW) & mask;
278 out_be64(&priv2->mfc_control_RW,
349 if ((in_be64(&priv2->mfc_control_RW) & MFC_CNTL_DMA_QUEUES_EMPTY) == 0) {
471 out_be64(&priv2->mfc_control_RW,
485 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
707 out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);
743 csa->priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
977 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |
991 POLL_WHILE_FALSE((in_be64(&priv2->mfc_control_RW) &
1270 if (csa->priv2.mfc_control_RW & MFC_CNTL_DECREMENTER_RUNNING) {
1399 out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);
1432 if ((csa->priv2.mfc_control_RW & MFC_CNTL_DMA_QUEUES_EMPTY_MASK) == 0) {
1741 out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);
2175 csa->priv2.mfc_control_RW = MFC_CNTL_RESUME_DMA_QUEUE |