Lines Matching defs:spu
32 #include <asm/spu.h>
40 struct spu *spu = ctx->spu;
41 struct spu_problem __iomem *prob = spu->problem;
45 spin_lock_irq(&spu->register_lock);
51 spin_unlock_irq(&spu->register_lock);
57 return in_be32(&ctx->spu->problem->mb_stat_R);
63 struct spu *spu = ctx->spu;
67 spin_lock_irq(&spu->register_lock);
68 stat = in_be32(&spu->problem->mb_stat_R);
79 spu_int_stat_clear(spu, 2, CLASS2_MAILBOX_INTR);
80 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
87 spu_int_stat_clear(spu, 2,
89 spu_int_mask_or(spu, 2,
93 spin_unlock_irq(&spu->register_lock);
99 struct spu *spu = ctx->spu;
100 struct spu_problem __iomem *prob = spu->problem;
101 struct spu_priv2 __iomem *priv2 = spu->priv2;
104 spin_lock_irq(&spu->register_lock);
111 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_INTR);
114 spin_unlock_irq(&spu->register_lock);
120 struct spu *spu = ctx->spu;
121 struct spu_problem __iomem *prob = spu->problem;
124 spin_lock_irq(&spu->register_lock);
132 spu_int_mask_or(spu, 2, CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR);
135 spin_unlock_irq(&spu->register_lock);
141 out_be32(&ctx->spu->problem->signal_notify1, data);
146 out_be32(&ctx->spu->problem->signal_notify2, data);
151 struct spu *spu = ctx->spu;
152 struct spu_priv2 __iomem *priv2 = spu->priv2;
155 spin_lock_irq(&spu->register_lock);
162 spin_unlock_irq(&spu->register_lock);
167 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 1) != 0);
172 struct spu *spu = ctx->spu;
173 struct spu_priv2 __iomem *priv2 = spu->priv2;
176 spin_lock_irq(&spu->register_lock);
183 spin_unlock_irq(&spu->register_lock);
188 return ((in_be64(&ctx->spu->priv2->spu_cfg_RW) & 2) != 0);
193 return in_be32(&ctx->spu->problem->spu_npc_RW);
198 out_be32(&ctx->spu->problem->spu_npc_RW, val);
203 return in_be32(&ctx->spu->problem->spu_status_R);
208 return ctx->spu->local_store;
213 out_be64(&ctx->spu->priv2->spu_privcntl_RW, val);
218 return in_be32(&ctx->spu->problem->spu_runcntl_RW);
223 spin_lock_irq(&ctx->spu->register_lock);
227 out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
228 spin_unlock_irq(&ctx->spu->register_lock);
233 spin_lock_irq(&ctx->spu->register_lock);
234 out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
235 while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
237 spin_unlock_irq(&ctx->spu->register_lock);
242 struct spu *spu = ctx->spu;
245 spin_lock_irq(&spu->register_lock);
246 sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
247 spu_mfc_sr1_set(spu, sr1);
248 spin_unlock_irq(&spu->register_lock);
253 struct spu *spu = ctx->spu;
256 spin_lock_irq(&spu->register_lock);
257 sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
258 spu_mfc_sr1_set(spu, sr1);
259 spin_unlock_irq(&spu->register_lock);
264 struct spu_problem __iomem *prob = ctx->spu->problem;
267 spin_lock_irq(&ctx->spu->register_lock);
275 spin_unlock_irq(&ctx->spu->register_lock);
281 return in_be32(&ctx->spu->problem->dma_tagstatus_R);
286 return in_be32(&ctx->spu->problem->dma_qstatus_R);
293 struct spu_problem __iomem *prob = ctx->spu->problem;
295 spin_lock_irq(&ctx->spu->register_lock);
303 spin_unlock_irq(&ctx->spu->register_lock);
317 struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;
319 if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))