Lines Matching refs:priv1
109 ctx->csa.priv1.int_stat_class2_RW &=
111 ctx->csa.priv1.int_mask_class2_RW |=
119 ctx->csa.priv1.int_stat_class2_RW &=
121 ctx->csa.priv1.int_mask_class2_RW |=
146 ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
176 ctx->csa.priv1.int_mask_class2_RW |=
315 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
316 csa->priv1.mfc_sr1_RW = sr1;
326 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
327 csa->priv1.mfc_sr1_RW = sr1;