Lines Matching defs:csa
54 ch0_cnt = ctx->csa.spu_chnlcnt_RW[0];
55 ch0_data = ctx->csa.spu_chnldata_RW[0];
56 ch1_data = ctx->csa.spu_chnldata_RW[1];
57 ctx->csa.spu_chnldata_RW[0] |= event;
59 ctx->csa.spu_chnlcnt_RW[0] = 1;
68 spin_lock(&ctx->csa.register_lock);
69 mbox_stat = ctx->csa.prob.mb_stat_R;
75 *data = ctx->csa.prob.pu_mb_R;
76 ctx->csa.prob.mb_stat_R &= ~(0x0000ff);
77 ctx->csa.spu_chnlcnt_RW[28] = 1;
81 spin_unlock(&ctx->csa.register_lock);
87 return ctx->csa.prob.mb_stat_R;
97 spin_lock_irq(&ctx->csa.register_lock);
98 stat = ctx->csa.prob.mb_stat_R;
109 ctx->csa.priv1.int_stat_class2_RW &=
111 ctx->csa.priv1.int_mask_class2_RW |=
119 ctx->csa.priv1.int_stat_class2_RW &=
121 ctx->csa.priv1.int_mask_class2_RW |=
125 spin_unlock_irq(&ctx->csa.register_lock);
133 spin_lock(&ctx->csa.register_lock);
134 if (ctx->csa.prob.mb_stat_R & 0xff0000) {
139 *data = ctx->csa.priv2.puint_mb_R;
140 ctx->csa.prob.mb_stat_R &= ~(0xff0000);
141 ctx->csa.spu_chnlcnt_RW[30] = 1;
146 ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
149 spin_unlock(&ctx->csa.register_lock);
157 spin_lock(&ctx->csa.register_lock);
158 if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) {
159 int slot = ctx->csa.spu_chnlcnt_RW[29];
160 int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8;
167 ctx->csa.spu_mailbox_data[slot] = data;
168 ctx->csa.spu_chnlcnt_RW[29] = ++slot;
169 ctx->csa.prob.mb_stat_R &= ~(0x00ff00);
170 ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8);
176 ctx->csa.priv1.int_mask_class2_RW |=
180 spin_unlock(&ctx->csa.register_lock);
186 return ctx->csa.spu_chnldata_RW[3];
191 spin_lock(&ctx->csa.register_lock);
192 if (ctx->csa.priv2.spu_cfg_RW & 0x1)
193 ctx->csa.spu_chnldata_RW[3] |= data;
195 ctx->csa.spu_chnldata_RW[3] = data;
196 ctx->csa.spu_chnlcnt_RW[3] = 1;
198 spin_unlock(&ctx->csa.register_lock);
203 return ctx->csa.spu_chnldata_RW[4];
208 spin_lock(&ctx->csa.register_lock);
209 if (ctx->csa.priv2.spu_cfg_RW & 0x2)
210 ctx->csa.spu_chnldata_RW[4] |= data;
212 ctx->csa.spu_chnldata_RW[4] = data;
213 ctx->csa.spu_chnlcnt_RW[4] = 1;
215 spin_unlock(&ctx->csa.register_lock);
222 spin_lock(&ctx->csa.register_lock);
223 tmp = ctx->csa.priv2.spu_cfg_RW;
228 ctx->csa.priv2.spu_cfg_RW = tmp;
229 spin_unlock(&ctx->csa.register_lock);
234 return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0);
241 spin_lock(&ctx->csa.register_lock);
242 tmp = ctx->csa.priv2.spu_cfg_RW;
247 ctx->csa.priv2.spu_cfg_RW = tmp;
248 spin_unlock(&ctx->csa.register_lock);
253 return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0);
258 return ctx->csa.prob.spu_npc_RW;
263 ctx->csa.prob.spu_npc_RW = val;
268 return ctx->csa.prob.spu_status_R;
273 return ctx->csa.lscsa->ls;
278 ctx->csa.priv2.spu_privcntl_RW = val;
283 return ctx->csa.prob.spu_runcntl_RW;
288 spin_lock(&ctx->csa.register_lock);
289 ctx->csa.prob.spu_runcntl_RW = val;
291 ctx->csa.prob.spu_status_R &=
297 ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
299 ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
301 spin_unlock(&ctx->csa.register_lock);
311 struct spu_state *csa = &ctx->csa;
314 spin_lock(&csa->register_lock);
315 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
316 csa->priv1.mfc_sr1_RW = sr1;
317 spin_unlock(&csa->register_lock);
322 struct spu_state *csa = &ctx->csa;
325 spin_lock(&csa->register_lock);
326 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
327 csa->priv1.mfc_sr1_RW = sr1;
328 spin_unlock(&csa->register_lock);
334 struct spu_problem_collapsed *prob = &ctx->csa.prob;
337 spin_lock(&ctx->csa.register_lock);
349 ctx->csa.prob.dma_tagstatus_R &= mask;
351 spin_unlock(&ctx->csa.register_lock);
358 return ctx->csa.prob.dma_tagstatus_R;
363 return ctx->csa.prob.dma_qstatus_R;
371 spin_lock(&ctx->csa.register_lock);
373 spin_unlock(&ctx->csa.register_lock);
380 ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;