Lines Matching defs:ctr
280 static void set_pm_event(u32 ctr, int event, u32 unit_mask)
289 pm_regs.pm07_cntrl[ctr] = CBE_COUNT_ALL_CYCLES;
290 p = &(pm_signal[ctr]);
297 pm_regs.pm07_cntrl[ctr] = 0;
307 p = &(pm_signal[ctr]);
313 pm_regs.pm07_cntrl[ctr] = 0;
314 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_COUNT_CYCLES(count_cycles);
315 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_POLARITY(polarity);
316 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_CONTROL(input_control);
341 pm_regs.pm07_cntrl[ctr] |= PM07_CTR_INPUT_MUX(signal_bit);
343 pm_regs.pm07_cntrl[ctr] = 0;
422 static inline void enable_ctr(u32 cpu, u32 ctr, u32 *pm07_cntrl)
425 pm07_cntrl[ctr] |= CBE_PM_CTR_ENABLE;
426 cbe_write_pm07_control(cpu, ctr, pm07_cntrl[ctr]);
559 static int cell_reg_setup_spu_cycles(struct op_counter_config *ctr,
562 spu_cycle_reset = ctr[0].count;
683 static int cell_reg_setup_spu_events(struct op_counter_config *ctr,
738 set_pm_event(0, ctr[0].event, ctr[0].unit_mask);
740 reset_value[0] = 0xFFFFFFFF - ctr[0].count;
752 static int cell_reg_setup_ppu(struct op_counter_config *ctr,
773 pmc_cntrl[0][i].evnts = ctr[i].event;
774 pmc_cntrl[0][i].masks = ctr[i].unit_mask;
775 pmc_cntrl[0][i].enabled = ctr[i].enabled;
787 if ((ctr[i].event >= 2100) && (ctr[i].event <= 2111))
788 pmc_cntrl[1][i].evnts = ctr[i].event + 19;
789 else if (ctr[i].event == 2203)
790 pmc_cntrl[1][i].evnts = ctr[i].event;
791 else if ((ctr[i].event >= 2200) && (ctr[i].event <= 2215))
792 pmc_cntrl[1][i].evnts = ctr[i].event + 16;
794 pmc_cntrl[1][i].evnts = ctr[i].event;
796 pmc_cntrl[1][i].masks = ctr[i].unit_mask;
797 pmc_cntrl[1][i].enabled = ctr[i].enabled;
815 reset_value[i] = 0xFFFFFFFF - ctr[i].count;
836 static int cell_reg_setup(struct op_counter_config *ctr,
868 if (ctr[0].event == SPU_CYCLES_EVENT_NUM) {
870 ret = cell_reg_setup_spu_cycles(ctr, sys, num_ctrs);
871 } else if ((ctr[0].event >= SPU_EVENT_NUM_START) &&
872 (ctr[0].event <= SPU_EVENT_NUM_STOP)) {
874 spu_cycle_reset = ctr[0].count;
882 cell_reg_setup_spu_events(ctr, sys, num_ctrs);
885 ret = cell_reg_setup_ppu(ctr, sys, num_ctrs);
1244 static int cell_global_start_spu_cycles(struct op_counter_config *ctr)
1334 static int cell_global_start_spu_events(struct op_counter_config *ctr)
1397 static int cell_global_start_ppu(struct op_counter_config *ctr)
1443 static int cell_global_start(struct op_counter_config *ctr)
1446 return cell_global_start_spu_cycles(ctr);
1448 return cell_global_start_spu_events(ctr);
1450 return cell_global_start_ppu(ctr);
1482 struct op_counter_config *ctr)
1516 && ctr[0].enabled)
1600 struct op_counter_config *ctr)
1641 && ctr[i].enabled) {
1673 struct op_counter_config *ctr)
1676 cell_handle_interrupt_ppu(regs, ctr);
1678 cell_handle_interrupt_spu(regs, ctr);