Lines Matching defs:cpuhw
251 static int power_check_constraints(struct cpu_hw_events *cpuhw,
270 cpuhw->alternatives[i]);
271 event_id[i] = cpuhw->alternatives[i][0];
273 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
274 &cpuhw->avalues[i][0]))
279 nv = (value | cpuhw->avalues[i][0]) +
280 (value & cpuhw->avalues[i][0] & addf);
282 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
283 cpuhw->amasks[i][0]) != 0)
286 mask |= cpuhw->amasks[i][0];
297 cpuhw->alternatives[i]);
299 ppmu->get_constraint(cpuhw->alternatives[i][j],
300 &cpuhw->amasks[i][j],
301 &cpuhw->avalues[i][j]);
320 nv = (value | cpuhw->avalues[i][j]) +
321 (value & cpuhw->avalues[i][j] & addf);
323 (((nv + tadd) ^ cpuhw->avalues[i][j])
324 & cpuhw->amasks[i][j]) == 0)
346 mask |= cpuhw->amasks[i][j];
354 event_id[i] = cpuhw->alternatives[i][choice[i]];
435 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
442 for (i = 0; i < cpuhw->n_limited; ++i) {
443 event = cpuhw->limited_counter[i];
454 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
461 for (i = 0; i < cpuhw->n_limited; ++i) {
462 event = cpuhw->limited_counter[i];
463 event->hw.idx = cpuhw->limited_hwidx[i];
481 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
485 if (!cpuhw->n_limited) {
504 freeze_limited_counters(cpuhw, pmc5, pmc6);
506 thaw_limited_counters(cpuhw, pmc5, pmc6);
522 struct cpu_hw_events *cpuhw;
528 cpuhw = &__get_cpu_var(cpu_hw_events);
530 if (!cpuhw->disabled) {
531 cpuhw->disabled = 1;
532 cpuhw->n_added = 0;
537 if (!cpuhw->pmcs_enabled) {
539 cpuhw->pmcs_enabled = 1;
545 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
547 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
557 write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
571 struct cpu_hw_events *cpuhw;
583 cpuhw = &__get_cpu_var(cpu_hw_events);
584 if (!cpuhw->disabled) {
588 cpuhw->disabled = 0;
596 if (!cpuhw->n_added) {
597 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
598 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
599 if (cpuhw->n_events == 0)
607 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
608 cpuhw->mmcr)) {
620 event = cpuhw->event[0];
622 cpuhw->mmcr[0] |= MMCR0_FCP;
624 cpuhw->mmcr[0] |= freeze_events_kernel;
626 cpuhw->mmcr[0] |= MMCR0_FCHV;
634 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
635 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
636 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
643 for (i = 0; i < cpuhw->n_events; ++i) {
644 event = cpuhw->event[i];
655 cpuhw->n_limited = n_lim = 0;
656 for (i = 0; i < cpuhw->n_events; ++i) {
657 event = cpuhw->event[i];
662 cpuhw->limited_counter[n_lim] = event;
663 cpuhw->limited_hwidx[n_lim] = idx;
678 cpuhw->n_limited = n_lim;
679 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
683 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
688 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
690 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
732 struct cpu_hw_events *cpuhw;
744 cpuhw = &__get_cpu_var(cpu_hw_events);
745 n0 = cpuhw->n_events;
748 cpuhw->event[n0] = event;
749 cpuhw->events[n0] = event->hw.config;
750 cpuhw->flags[n0] = event->hw.event_base;
757 if (cpuhw->group_flag & PERF_EVENT_TXN)
760 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
762 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
764 event->hw.config = cpuhw->events[n0];
767 ++cpuhw->n_events;
768 ++cpuhw->n_added;
782 struct cpu_hw_events *cpuhw;
791 cpuhw = &__get_cpu_var(cpu_hw_events);
792 for (i = 0; i < cpuhw->n_events; ++i) {
793 if (event == cpuhw->event[i]) {
794 while (++i < cpuhw->n_events) {
795 cpuhw->event[i-1] = cpuhw->event[i];
796 cpuhw->events[i-1] = cpuhw->events[i];
797 cpuhw->flags[i-1] = cpuhw->flags[i];
799 --cpuhw->n_events;
800 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
809 for (i = 0; i < cpuhw->n_limited; ++i)
810 if (event == cpuhw->limited_counter[i])
812 if (i < cpuhw->n_limited) {
813 while (++i < cpuhw->n_limited) {
814 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
815 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
817 --cpuhw->n_limited;
819 if (cpuhw->n_events == 0) {
821 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
862 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
864 cpuhw->group_flag |= PERF_EVENT_TXN;
865 cpuhw->n_txn_start = cpuhw->n_events;
875 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
877 cpuhw->group_flag &= ~PERF_EVENT_TXN;
887 struct cpu_hw_events *cpuhw;
892 cpuhw = &__get_cpu_var(cpu_hw_events);
893 n = cpuhw->n_events;
894 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
896 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
900 for (i = cpuhw->n_txn_start; i < n; ++i)
901 cpuhw->event[i]->hw.config = cpuhw->events[i];
903 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1026 struct cpu_hw_events *cpuhw;
1100 cpuhw = &get_cpu_var(cpu_hw_events);
1101 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1234 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1240 if (cpuhw->n_limited)
1241 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
1252 for (i = 0; i < cpuhw->n_events; ++i) {
1253 event = cpuhw->event[i];
1280 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
1290 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
1294 memset(cpuhw, 0, sizeof(*cpuhw));
1295 cpuhw->mmcr[0] = MMCR0_FC;