Lines Matching refs:r4
92 rlwinm r4,r7,0,17,15
93 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
95 mtmsr r4
99 rlwinm r4,r8,0,12,10 /* Turn off HID0[DPM] */
101 mtspr SPRN_HID0,r4 /* Disable DPM */
104 /* Get the current enable bit of the L2CR into r4 */
105 mfspr r4,SPRN_L2CR
113 rlwinm. r4,r4,0,0,0
136 mfspr r4,SPRN_MSSCR0
137 rlwinm r4,r4,0,0,29
139 mtspr SPRN_MSSCR0,r4
142 lis r4,KERNELBASE@h
143 dcbf 0,r4
144 dcbf 0,r4
145 dcbf 0,r4
146 dcbf 0,r4
151 lis r4,0x0002
152 mtctr r4
153 li r4,0
155 lwzx r0,r0,r4
156 addi r4,r4,32 /* Go to start of next cache line */
161 lis r4,0x0002
162 mtctr r4
163 li r4,0
166 dcbf 0,r4
167 addi r4,r4,32 /* Go to start of next cache line */
200 andis. r4,r3,0x0020
207 rlwinm. r4,r3,0,31,31
271 rlwinm r4,r7,0,17,15
272 rlwinm r4,r4,0,28,26 /* Turn off DR bit */
274 mtmsr r4
281 /* Get the current enable bit of the L3CR into r4 */
282 mfspr r4,SPRN_L3CR
290 rlwinm. r4,r4,0,0,0
298 lis r4,0x0008
299 mtctr r4
300 li r4,0
302 lwzx r0,r0,r4
303 dcbf 0,r4
304 addi r4,r4,32 /* Go to start of next cache line */
334 andi. r4,r3,0x0400