Lines Matching refs:ull
432 #define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
433 #define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
434 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
435 #define MFC_CNTL_SUSPEND_MASK (1ull << 4)
436 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
437 #define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
438 #define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
439 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
440 #define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
441 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
442 #define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
443 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
444 #define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
445 #define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
446 #define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
447 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
448 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
449 #define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
450 #define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
451 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
452 #define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
453 #define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
454 #define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
632 #define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
633 #define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
638 #define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
683 #define SPU_ECC_CNTL_E (1ull << 0ull)
686 #define SPU_ECC_CNTL_S (1ull << 1ull)
689 #define SPU_ECC_CNTL_B (1ull << 2ull)
692 #define SPU_ECC_CNTL_I_SHIFT 3ull
693 #define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
695 #define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
696 #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
697 #define SPU_ECC_CNTL_D (1ull << 5ull)
701 #define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
702 #define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
703 #define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
704 #define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
705 #define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
706 #define SPU_ECC_DATA_ERROR (1ull << 5ul)
707 #define SPU_ECC_DMA_ERROR (1ull << 6ul)
708 #define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
711 #define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
712 #define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)