Lines Matching refs:__MASK
52 #define __MASK(X) (1<<(X))
54 #define __MASK(X) (1UL<<(X))
58 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
59 #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
60 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
68 #define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
69 #define MSR_VSX __MASK(MSR_VSX_LG) /* Enable VSX */
70 #define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
71 #define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
72 #define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
73 #define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
74 #define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
75 #define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
76 #define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
77 #define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
78 #define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
79 #define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
80 #define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
81 #define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
82 #define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
83 #define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
84 #define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
85 #define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
86 #define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
87 #define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
88 #define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
90 #define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
92 #define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
93 #define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */