Lines Matching refs:__be32
27 __be32 iadd; /* I-RAM Address Register */
28 __be32 idata; /* I-RAM Data Register */
34 __be32 qicr;
35 __be32 qivec;
36 __be32 qripnr;
37 __be32 qipnr;
38 __be32 qipxcc;
39 __be32 qipycc;
40 __be32 qipwcc;
41 __be32 qipzcc;
42 __be32 qimr;
43 __be32 qrimr;
44 __be32 qicnr;
46 __be32 qiprta;
47 __be32 qiprtb;
49 __be32 qricr;
51 __be32 qhivec;
57 __be32 cecr; /* QE command register */
58 __be32 ceccr; /* QE controller configuration register */
59 __be32 cecdr; /* QE command data register */
64 __be32 cetscr; /* QE time-stamp timer control register */
65 __be32 cetsr1; /* QE time-stamp register 1 */
66 __be32 cetsr2; /* QE time-stamp register 2 */
68 __be32 cevter; /* QE virtual tasks event register */
69 __be32 cevtmr; /* QE virtual tasks mask register */
89 __be32 ceurnr; /* QE microcode revision number register */
95 __be32 cmxgcr; /* CMX general clock route register */
96 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
97 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
98 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
99 __be32 cmxucr[4]; /* CMX UCCx clock route registers */
100 __be32 cmxupcr; /* CMX UPC clock route register */
136 __be32 brgc[16]; /* BRG configuration registers */
143 __be32 spmode; /* SPI mode register */
153 __be32 spitd; /* SPI transmit data register (cpu mode) */
154 __be32 spird; /* SPI receive data register (cpu mode) */
200 __be32 siml1; /* SI1 multiframe limit register */
233 __be32 mcce; /* MCC event register */
234 __be32 mccm; /* MCC mask register */
235 __be32 mccf; /* MCC configuration register */
236 __be32 merl; /* MCC emergency request level register */
242 __be32 gumr_l; /* UCCx general mode register (low) */
243 __be32 gumr_h; /* UCCx general mode register (high) */
261 __be32 gumr; /* UCCx general mode register */
262 __be32 upsmr; /* UCCx protocol-specific mode register */
267 __be32 ucce; /* UCCx event register */
268 __be32 uccm; /* UCCx mask register */
271 __be32 urfb; /* UCC receive FIFO base */
277 __be32 utfb; /* UCC transmit FIFO base */
286 __be32 urtry; /* UCC retry counter register */
301 __be32 upgcr; /* UTOPIA/POS general configuration register */
302 __be32 uplpa; /* UTOPIA/POS last PHY address */
303 __be32 uphec; /* ATM HEC register */
304 __be32 upuc; /* UTOPIA/POS UCC configuration */
305 __be32 updc1; /* UTOPIA/POS device 1 configuration */
306 __be32 updc2; /* UTOPIA/POS device 2 configuration */
307 __be32 updc3; /* UTOPIA/POS device 3 configuration */
308 __be32 updc4; /* UTOPIA/POS device 4 configuration */
309 __be32 upstpa; /* UTOPIA/POS STPA threshold */
311 __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */
312 __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */
313 __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */
314 __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */
315 __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */
316 __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */
317 __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */
318 __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */
319 __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */
320 __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */
321 __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */
322 __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */
323 __be32 upde1; /* UTOPIA/POS device 1 event */
324 __be32 upde2; /* UTOPIA/POS device 2 event */
325 __be32 upde3; /* UTOPIA/POS device 3 event */
326 __be32 upde4; /* UTOPIA/POS device 4 event */
348 __be32 uper1; /* Device 1 port enable register */
349 __be32 uper2; /* Device 2 port enable register */
350 __be32 uper3; /* Device 3 port enable register */
351 __be32 uper4; /* Device 4 port enable register */
357 __be32 sdsr; /* Serial DMA status register */
358 __be32 sdmr; /* Serial DMA mode register */
359 __be32 sdtr1; /* SDMA system bus threshold register */
360 __be32 sdtr2; /* SDMA secondary bus threshold register */
361 __be32 sdhy1; /* SDMA system bus hysteresis register */
362 __be32 sdhy2; /* SDMA secondary bus hysteresis register */
363 __be32 sdta1; /* SDMA system bus address register */
364 __be32 sdta2; /* SDMA secondary bus address register */
365 __be32 sdtm1; /* SDMA system bus MSNUM register */
366 __be32 sdtm2; /* SDMA secondary bus MSNUM register */
368 __be32 sdaqr; /* SDMA address bus qualify register */
369 __be32 sdaqmr; /* SDMA address bus qualify mask register */
371 __be32 sdebcr; /* SDMA CAM entries base register */
377 __be32 bpdcr; /* Breakpoint debug command register */
378 __be32 bpdsr; /* Breakpoint debug status register */
379 __be32 bpdmr; /* Breakpoint debug mask register */
380 __be32 bprmrr0; /* Breakpoint request mode risc register 0 */
381 __be32 bprmrr1; /* Breakpoint request mode risc register 1 */
383 __be32 bprmtr0; /* Breakpoint request mode trb register 0 */
384 __be32 bprmtr1; /* Breakpoint request mode trb register 1 */
386 __be32 bprmir; /* Breakpoint request mode immediate register */
387 __be32 bprmsr; /* Breakpoint request mode serial register */
388 __be32 bpemr; /* Breakpoint exit mode register */
397 __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */
399 __be32 ibcr0;
400 __be32 ibs0;
401 __be32 ibcnr0;
403 __be32 ibcr1;
404 __be32 ibs1;
405 __be32 ibcnr1;
406 __be32 npcr;
407 __be32 dbcr;
408 __be32 dbar;
409 __be32 dbamr;
410 __be32 dbsr;
411 __be32 dbcnr;
413 __be32 dbdr_h;
414 __be32 dbdr_l;
415 __be32 dbdmr_h;
416 __be32 dbdmr_l;
417 __be32 bsr;
418 __be32 bor;
419 __be32 bior;
421 __be32 iatr[4];
422 __be32 eccr; /* Exception control configuration register */
423 __be32 eicr;