Lines Matching refs:ushort
73 #define CPM_CR_START_IDMA ((ushort)0x0009)
167 ushort smc_rbase; /* Rx Buffer descriptor base address */
168 ushort smc_tbase; /* Tx Buffer descriptor base address */
171 ushort smc_mrblr; /* Max receive buffer length */
174 ushort smc_rbptr; /* Internal */
175 ushort smc_ibc; /* Internal */
179 ushort smc_tbptr; /* Internal */
180 ushort smc_tbc; /* Internal */
182 ushort smc_maxidl; /* Maximum idle characters */
183 ushort smc_tmpidl; /* Temporary idle counter */
184 ushort smc_brklen; /* Last received break length */
185 ushort smc_brkec; /* rcv'd break condition counter */
186 ushort smc_brkcr; /* xmt break count register */
187 ushort smc_rmask; /* Temporary bit mask */
193 #define SMCMR_REN ((ushort)0x0001)
194 #define SMCMR_TEN ((ushort)0x0002)
195 #define SMCMR_DM ((ushort)0x000c)
196 #define SMCMR_SM_GCI ((ushort)0x0000)
197 #define SMCMR_SM_UART ((ushort)0x0020)
198 #define SMCMR_SM_TRANS ((ushort)0x0030)
199 #define SMCMR_SM_MASK ((ushort)0x0030)
200 #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
202 #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
204 #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
205 #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
299 #define SCC_TODR_TOD ((ushort)0x8000)
309 ushort scc_rbase; /* Rx Buffer descriptor base address */
310 ushort scc_tbase; /* Tx Buffer descriptor base address */
313 ushort scc_mrblr; /* Max receive buffer length */
316 ushort scc_rbptr; /* Internal */
317 ushort scc_ibc; /* Internal */
321 ushort scc_tbptr; /* Internal */
322 ushort scc_tbc; /* Internal */
342 ushort sen_pads; /* Tx short frame pad character */
343 ushort sen_retlim; /* Retry limit threshold */
344 ushort sen_retcnt; /* Retry limit counter */
345 ushort sen_maxflr; /* maximum frame length register */
346 ushort sen_minflr; /* minimum frame length register */
347 ushort sen_maxd1; /* maximum DMA1 length */
348 ushort sen_maxd2; /* maximum DMA2 length */
349 ushort sen_maxd; /* Rx max DMA */
350 ushort sen_dmacnt; /* Rx DMA counter */
351 ushort sen_maxb; /* Max BD byte count */
352 ushort sen_gaddr1; /* Group address filter */
353 ushort sen_gaddr2;
354 ushort sen_gaddr3;
355 ushort sen_gaddr4;
360 ushort sen_tbuf0bcnt; /* Internal */
361 ushort sen_paddrh; /* physical address (MSB) */
362 ushort sen_paddrm;
363 ushort sen_paddrl; /* physical address (LSB) */
364 ushort sen_pper; /* persistence */
365 ushort sen_rfbdptr; /* Rx first BD pointer */
366 ushort sen_tfbdptr; /* Tx first BD pointer */
367 ushort sen_tlbdptr; /* Tx last BD pointer */
372 ushort sen_tbuf1bcnt; /* Internal */
373 ushort sen_txlen; /* Tx Frame length counter */
374 ushort sen_iaddr1; /* Individual address filter */
375 ushort sen_iaddr2;
376 ushort sen_iaddr3;
377 ushort sen_iaddr4;
378 ushort sen_boffcnt; /* Backoff counter */
383 ushort sen_taddrh; /* temp address (MSB) */
384 ushort sen_taddrm;
385 ushort sen_taddrl; /* temp address (LSB) */
391 #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
392 #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
393 #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
394 #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
395 #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
396 #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
400 #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
401 #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
402 #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
403 #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
404 #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
405 #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
406 #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
407 #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
408 #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
409 #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
410 #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
411 #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
412 #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
420 ushort scc_maxidl; /* Maximum idle chars */
421 ushort scc_idlc; /* temp idle counter */
422 ushort scc_brkcr; /* Break count register */
423 ushort scc_parec; /* receive parity error counter */
424 ushort scc_frmec; /* receive framing error counter */
425 ushort scc_nosec; /* receive noise counter */
426 ushort scc_brkec; /* receive break condition counter */
427 ushort scc_brkln; /* last received break length */
428 ushort scc_uaddr1; /* UART address character 1 */
429 ushort scc_uaddr2; /* UART address character 2 */
430 ushort scc_rtemp; /* Temp storage */
431 ushort scc_toseq; /* Transmit out of sequence char */
432 ushort scc_char1; /* control character 1 */
433 ushort scc_char2; /* control character 2 */
434 ushort scc_char3; /* control character 3 */
435 ushort scc_char4; /* control character 4 */
436 ushort scc_char5; /* control character 5 */
437 ushort scc_char6; /* control character 6 */
438 ushort scc_char7; /* control character 7 */
439 ushort scc_char8; /* control character 8 */
440 ushort scc_rccm; /* receive control character mask */
441 ushort scc_rccr; /* receive control character register */
442 ushort scc_rlbc; /* receive last break character */
447 #define UART_SCCM_GLR ((ushort)0x1000)
448 #define UART_SCCM_GLT ((ushort)0x0800)
449 #define UART_SCCM_AB ((ushort)0x0200)
450 #define UART_SCCM_IDL ((ushort)0x0100)
451 #define UART_SCCM_GRA ((ushort)0x0080)
452 #define UART_SCCM_BRKE ((ushort)0x0040)
453 #define UART_SCCM_BRKS ((ushort)0x0020)
454 #define UART_SCCM_CCR ((ushort)0x0008)
455 #define UART_SCCM_BSY ((ushort)0x0004)
456 #define UART_SCCM_TX ((ushort)0x0002)
457 #define UART_SCCM_RX ((ushort)0x0001)
461 #define SCU_PSMR_FLC ((ushort)0x8000)
462 #define SCU_PSMR_SL ((ushort)0x4000)
463 #define SCU_PSMR_CL ((ushort)0x3000)
464 #define SCU_PSMR_UM ((ushort)0x0c00)
465 #define SCU_PSMR_FRZ ((ushort)0x0200)
466 #define SCU_PSMR_RZS ((ushort)0x0100)
467 #define SCU_PSMR_SYN ((ushort)0x0080)
468 #define SCU_PSMR_DRT ((ushort)0x0040)
469 #define SCU_PSMR_PEN ((ushort)0x0010)
470 #define SCU_PSMR_RPM ((ushort)0x000c)
471 #define SCU_PSMR_REVP ((ushort)0x0008)
472 #define SCU_PSMR_TPM ((ushort)0x0003)
473 #define SCU_PSMR_TEVP ((ushort)0x0002)
518 ushort fcc_riptr; /* Rx Internal temp pointer */
519 ushort fcc_tiptr; /* Tx Internal temp pointer */
520 ushort fcc_res1;
521 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
524 ushort fcc_rbdstat; /* RxBD status */
525 ushort fcc_rbdlen; /* RxBD down counter */
529 ushort fcc_tbdstat; /* TxBD status */
530 ushort fcc_tbdlen; /* TxBD down counter */
551 ushort fen_retlim; /* Retry limit */
552 ushort fen_retcnt; /* Retry counter */
553 ushort fen_pper; /* Persistence */
554 ushort fen_boffcnt; /* backoff counter */
557 ushort fen_tfcstat; /* out of sequence TxBD */
558 ushort fen_tfclen;
560 ushort fen_mflr; /* Maximum frame length (1518) */
561 ushort fen_paddrh; /* MAC address */
562 ushort fen_paddrm;
563 ushort fen_paddrl;
564 ushort fen_ibdcount; /* Internal BD counter */
565 ushort fen_ibdstart; /* Internal BD start pointer */
566 ushort fen_ibdend; /* Internal BD end pointer */
567 ushort fen_txlen; /* Internal Tx frame length counter */
571 ushort fen_minflr; /* Minimum frame length (64) */
572 ushort fen_taddrh; /* Filter transfer MAC address */
573 ushort fen_taddrm;
574 ushort fen_taddrl;
575 ushort fen_padptr; /* Pointer to pad byte buffer */
576 ushort fen_cftype; /* control frame type */
577 ushort fen_cfrange; /* control frame range */
578 ushort fen_maxb; /* maximum BD count */
579 ushort fen_maxd1; /* Max DMA1 length (1520) */
580 ushort fen_maxd2; /* Max DMA2 length (1520) */
581 ushort fen_maxd; /* internal max DMA count */
582 ushort fen_dmacnt; /* internal DMA counter */
598 ushort fen_rfthr; /* Received frames threshold */
599 ushort fen_rfcnt; /* Received frames count */
604 #define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
605 #define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
606 #define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
607 #define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
608 #define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
609 #define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
610 #define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
611 #define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
632 ushort iic_rbase; /* Rx Buffer descriptor base address */
633 ushort iic_tbase; /* Tx Buffer descriptor base address */
636 ushort iic_mrblr; /* Max receive buffer length */
639 ushort iic_rbptr; /* Internal */
640 ushort iic_rbc; /* Internal */
644 ushort iic_tbptr; /* Internal */
645 ushort iic_tbc; /* Internal */
652 ushort ibase; /* IDMA buffer descriptor table base address */
653 ushort dcm; /* DMA channel mode */
654 ushort ibdptr; /* IDMA current buffer descriptor pointer */
655 ushort dpr_buf; /* IDMA transfer buffer base address */
656 ushort buf_inv; /* internal buffer inventory */
657 ushort ss_max; /* steady-state maximum transfer size */
658 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
659 ushort sts; /* source transfer size */
660 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
661 ushort seob; /* source end of burst */
662 ushort deob; /* destination end of burst */
663 ushort dts; /* destination transfer size */
664 ushort ret_add; /* return address when working in ERM=1 mode */
665 ushort res0; /* reserved */
675 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
676 #define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
677 #define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
678 #define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
679 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
680 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
681 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
682 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
683 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
684 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
685 #define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
686 #define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
687 #define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
688 #define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
689 #define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
690 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
691 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
692 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */