Lines Matching defs:bridge_base
26 static u8 *bridge_base;
53 mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
58 enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
60 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
77 mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,
111 mv64x60_config_cpu2pci_window(bridge_base, bus,
117 out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),
126 mem_size = mv64x60_get_mem_size(bridge_base);
142 if (bridge_base != 0) {
143 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
145 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
147 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
149 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
151 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
153 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
155 temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
157 out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
159 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
161 out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
163 temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
165 out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
167 out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
183 bridge_base = mv64x60_get_bridge_base();