Lines Matching refs:ir
767 mips_instruction ir;
798 ir = dec_insn.next_insn; /* process delay slot instr */
801 ir = dec_insn.insn; /* process current instr */
814 (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL))
820 switch (MIPSInst_OPCODE(ir)) {
822 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
823 MIPSInst_SIMM(ir));
838 DITOREG(val, MIPSInst_RT(ir));
843 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
844 MIPSInst_SIMM(ir));
848 DIFROMREG(val, MIPSInst_RT(ir));
863 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
864 MIPSInst_SIMM(ir));
878 SITOREG(val, MIPSInst_RT(ir));
883 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
884 MIPSInst_SIMM(ir));
888 SIFROMREG(val, MIPSInst_RT(ir));
903 switch (MIPSInst_RS(ir)) {
908 if (MIPSInst_RT(ir) != 0) {
909 DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
910 MIPSInst_RD(ir));
916 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
922 if (MIPSInst_RT(ir) != 0) {
923 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
924 MIPSInst_RD(ir));
930 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
937 if (MIPSInst_RD(ir) == FPCREG_CSR) {
944 MIPSInst_RT(ir), value);
947 else if (MIPSInst_RD(ir) == FPCREG_RID)
951 if (MIPSInst_RT(ir))
952 xcp->regs[MIPSInst_RT(ir)] = value;
960 if (MIPSInst_RT(ir) == 0)
963 value = xcp->regs[MIPSInst_RT(ir)];
967 if (MIPSInst_RD(ir) == FPCREG_CSR) {
971 MIPSInst_RT(ir), value);
995 cond = ctx->fcr31 & fpucondbit[MIPSInst_RT(ir) >> 2];
999 switch (MIPSInst_RT(ir) & 3) {
1021 contpc = MIPSInst_SIMM(ir);
1022 ir = dec_insn.next_insn;
1028 (micro_mips32_to_mips32((union mips_instruction *)&ir) == SIGILL)) {
1033 ir = (ir & (~0xffff)) | MM_NOP16;
1039 return mips_dsemul(xcp, ir, contpc);
1044 switch (MIPSInst_OPCODE(ir)) {
1059 if (MIPSInst_FUNC(ir) == movc_op)
1069 return mips_dsemul(xcp, ir, contpc);
1090 if (!(MIPSInst_RS(ir) & 0x10))
1096 if ((sig = fpu_emu(xcp, ctx, ir)))
1104 int sig = fpux_emu(xcp, ctx, ir, fault_addr);
1113 if (MIPSInst_FUNC(ir) != movc_op)
1115 cond = fpucondbit[MIPSInst_RT(ir) >> 2];
1116 if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
1117 xcp->regs[MIPSInst_RD(ir)] =
1118 xcp->regs[MIPSInst_RS(ir)];
1201 mips_instruction ir, void *__user *fault_addr)
1207 switch (MIPSInst_FMA_FFMT(ir)) {
1215 switch (MIPSInst_FUNC(ir)) {
1217 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1218 xcp->regs[MIPSInst_FT(ir)]);
1231 SITOREG(val, MIPSInst_FD(ir));
1235 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1236 xcp->regs[MIPSInst_FT(ir)]);
1240 SIFROMREG(val, MIPSInst_FS(ir));
1267 SPFROMREG(fr, MIPSInst_FR(ir));
1268 SPFROMREG(fs, MIPSInst_FS(ir));
1269 SPFROMREG(ft, MIPSInst_FT(ir));
1271 SPTOREG(fd, MIPSInst_FD(ir));
1304 switch (MIPSInst_FUNC(ir)) {
1306 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1307 xcp->regs[MIPSInst_FT(ir)]);
1320 DITOREG(val, MIPSInst_FD(ir));
1324 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
1325 xcp->regs[MIPSInst_FT(ir)]);
1328 DIFROMREG(val, MIPSInst_FS(ir));
1355 DPFROMREG(fr, MIPSInst_FR(ir));
1356 DPFROMREG(fs, MIPSInst_FS(ir));
1357 DPFROMREG(ft, MIPSInst_FT(ir));
1359 DPTOREG(fd, MIPSInst_FD(ir));
1369 if (MIPSInst_FUNC(ir) != pfetch_op) {
1389 mips_instruction ir)
1404 switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
1411 switch (MIPSInst_FUNC(ir)) {
1442 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1444 ((MIPSInst_FT(ir) & 1) != 0))
1446 SPFROMREG(rv.s, MIPSInst_FS(ir));
1449 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1451 SPFROMREG(rv.s, MIPSInst_FS(ir));
1454 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1456 SPFROMREG(rv.s, MIPSInst_FS(ir));
1467 SPFROMREG(rv.s, MIPSInst_FS(ir));
1475 SPFROMREG(fs, MIPSInst_FS(ir));
1476 SPFROMREG(ft, MIPSInst_FT(ir));
1485 SPFROMREG(fs, MIPSInst_FS(ir));
1508 SPFROMREG(fs, MIPSInst_FS(ir));
1516 SPFROMREG(fs, MIPSInst_FS(ir));
1530 SPFROMREG(fs, MIPSInst_FS(ir));
1531 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1543 SPFROMREG(fs, MIPSInst_FS(ir));
1556 SPFROMREG(fs, MIPSInst_FS(ir));
1557 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1566 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1567 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1570 SPFROMREG(fs, MIPSInst_FS(ir));
1571 SPFROMREG(ft, MIPSInst_FT(ir));
1596 switch (MIPSInst_FUNC(ir)) {
1627 cond = fpucondbit[MIPSInst_FT(ir) >> 2];
1629 ((MIPSInst_FT(ir) & 1) != 0))
1631 DPFROMREG(rv.d, MIPSInst_FS(ir));
1634 if (xcp->regs[MIPSInst_FT(ir)] != 0)
1636 DPFROMREG(rv.d, MIPSInst_FS(ir));
1639 if (xcp->regs[MIPSInst_FT(ir)] == 0)
1641 DPFROMREG(rv.d, MIPSInst_FS(ir));
1654 DPFROMREG(rv.d, MIPSInst_FS(ir));
1661 DPFROMREG(fs, MIPSInst_FS(ir));
1662 DPFROMREG(ft, MIPSInst_FT(ir));
1670 DPFROMREG(fs, MIPSInst_FS(ir));
1679 DPFROMREG(fs, MIPSInst_FS(ir));
1690 DPFROMREG(fs, MIPSInst_FS(ir));
1704 DPFROMREG(fs, MIPSInst_FS(ir));
1705 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1717 DPFROMREG(fs, MIPSInst_FS(ir));
1730 DPFROMREG(fs, MIPSInst_FS(ir));
1731 ieee754_csr.rm = ieee_rm[modeindex(MIPSInst_FUNC(ir))];
1740 if (MIPSInst_FUNC(ir) >= fcmp_op) {
1741 unsigned cmpop = MIPSInst_FUNC(ir) - fcmp_op;
1744 DPFROMREG(fs, MIPSInst_FS(ir));
1745 DPFROMREG(ft, MIPSInst_FT(ir));
1769 switch (MIPSInst_FUNC(ir)) {
1772 SPFROMREG(fs, MIPSInst_FS(ir));
1778 SPFROMREG(fs, MIPSInst_FS(ir));
1790 switch (MIPSInst_FUNC(ir)) {
1793 rv.s = ieee754sp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1798 rv.d = ieee754dp_flong(ctx->fpr[MIPSInst_FS(ir)]);
1831 cond = fpucondbit[MIPSInst_FD(ir) >> 2];
1842 DPTOREG(rv.d, MIPSInst_FD(ir));
1845 SPTOREG(rv.s, MIPSInst_FD(ir));
1848 SITOREG(rv.w, MIPSInst_FD(ir));
1852 DITOREG(rv.l, MIPSInst_FD(ir));