Lines Matching refs:MSP_SLP_BASE
49 #define MSP_SLP_BASE 0x1c000000
51 #define MSP_RST_BASE (MSP_SLP_BASE + 0x10)
55 #define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C)
57 #define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054)
59 #define MSP_UART0_BASE (MSP_SLP_BASE + 0x100)
61 #define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120)
63 #define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160)
173 #define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00)
175 #define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04)
177 #define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08)
179 #define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C)
183 #define RST_STS_REG regptr(MSP_SLP_BASE + 0x10)
185 #define RST_SET_REG regptr(MSP_SLP_BASE + 0x14)
187 #define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18)
191 #define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C)
193 #define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20)
195 /* reserved (MSP_SLP_BASE + 0x24) */
196 /* reserved (MSP_SLP_BASE + 0x28) */
197 #define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C)
199 #define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30)
201 #define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34)
203 #define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38)
205 /* reserved (MSP_SLP_BASE + 0x3C) */
206 #define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40)
208 #define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44)
210 #define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48)
214 #define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
216 #define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
218 #define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78)
220 #define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C)
224 #define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80)
226 #define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84)
228 #define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88)
230 #define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
233 #define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90)
235 #define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94)
237 #define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98)
239 #define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
242 #define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0)
244 #define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4)
246 #define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8)
248 #define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
251 #define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0)
253 #define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4)
255 #define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8)
257 #define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
260 #define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0)
262 #define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4)
264 #define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8)
266 #define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
269 #define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0)
271 #define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4)
273 #define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8)
275 #define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
279 #define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
283 #define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
293 #define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140)
295 #define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144)
297 #define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148)
299 #define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C)
303 #define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150)
305 #define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154)
307 #define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158)
309 #define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C)
313 #define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C)
317 #define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180)
319 #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184)
322 #define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188)
326 #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190)
328 #define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194)
330 #define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198)
332 #define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C)
336 #define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0)
338 #define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4)
340 #define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8)
342 #define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC)
345 #define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4)
349 #define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200)
351 #define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204)
353 #define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208)
355 #define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C)
526 #define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c)