Lines Matching refs:bootcr
173 u32 *bootcr, u32 bus_clock)
184 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
199 if (*bootcr & BOOT_PLL_BYPASS)
219 u32 *bootcr, u32 frequency)
224 switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
252 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
258 &clocks->bus, bootcr, AR7_AFE_CLOCK);
260 if (*bootcr & BOOT_PLL_ASYNC_MODE)
262 &clocks->cpu, bootcr, AR7_AFE_CLOCK);
268 bootcr, dsp_clk.rate);
271 iounmap(bootcr);
308 static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
310 if (*bootcr & BOOT_PLL_ASYNC_MODE)
320 if (*bootcr & BOOT_PLL_2TO1_MODE)
336 u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
344 cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
345 dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
347 if (*bootcr & BOOT_PLL_ASYNC_MODE) {
369 if (*bootcr & BOOT_PLL_2TO1_MODE) {
414 iounmap(bootcr);