Lines Matching refs:au_writel
86 au_writel(0, 0xb0100004);
88 au_writel(0, USB_HOST_CONFIG);
92 au_writel(0, USBD_ENABLE);
97 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
135 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
136 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
137 au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
138 au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
140 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
143 au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
147 au_writel(sleep_usb[0], USB_HOST_CONFIG);
148 au_writel(sleep_usb[1], USBD_ENABLE);
152 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
156 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
158 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
163 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
164 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
165 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
166 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
167 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
168 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
169 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
170 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
171 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
172 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
173 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
174 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
181 au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
182 au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
183 au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
184 au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
185 au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
186 au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
187 au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();