Lines Matching defs:pvr
19 unsigned pvr[12];
22 /* The following taken from Xilinx's standalone BSP pvr.h */
123 #define PVR_IS_FULL(pvr) (pvr.pvr[0] & PVR0_PVR_FULL_MASK)
124 #define PVR_USE_BARREL(pvr) (pvr.pvr[0] & PVR0_USE_BARREL_MASK)
125 #define PVR_USE_DIV(pvr) (pvr.pvr[0] & PVR0_USE_DIV_MASK)
126 #define PVR_USE_HW_MUL(pvr) (pvr.pvr[0] & PVR0_USE_HW_MUL_MASK)
127 #define PVR_USE_FPU(pvr) (pvr.pvr[0] & PVR0_USE_FPU_MASK)
128 #define PVR_USE_FPU2(pvr) (pvr.pvr[2] & PVR2_USE_FPU2_MASK)
129 #define PVR_USE_ICACHE(pvr) (pvr.pvr[0] & PVR0_USE_ICACHE_MASK)
130 #define PVR_USE_DCACHE(pvr) (pvr.pvr[0] & PVR0_USE_DCACHE_MASK)
131 #define PVR_VERSION(pvr) ((pvr.pvr[0] & PVR0_VERSION_MASK) >> 8)
132 #define PVR_USER1(pvr) (pvr.pvr[0] & PVR0_USER1_MASK)
133 #define PVR_USER2(pvr) (pvr.pvr[1] & PVR1_USER2_MASK)
135 #define PVR_D_OPB(pvr) (pvr.pvr[2] & PVR2_D_OPB_MASK)
136 #define PVR_D_LMB(pvr) (pvr.pvr[2] & PVR2_D_LMB_MASK)
137 #define PVR_I_OPB(pvr) (pvr.pvr[2] & PVR2_I_OPB_MASK)
138 #define PVR_I_LMB(pvr) (pvr.pvr[2] & PVR2_I_LMB_MASK)
139 #define PVR_INTERRUPT_IS_EDGE(pvr) \
140 (pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK)
141 #define PVR_EDGE_IS_POSITIVE(pvr) \
142 (pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK)
143 #define PVR_USE_MSR_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_MSR_INSTR)
144 #define PVR_USE_PCMP_INSTR(pvr) (pvr.pvr[2] & PVR2_USE_PCMP_INSTR)
145 #define PVR_AREA_OPTIMISED(pvr) (pvr.pvr[2] & PVR2_AREA_OPTIMISED)
146 #define PVR_USE_MUL64(pvr) (pvr.pvr[2] & PVR2_USE_MUL64_MASK)
147 #define PVR_OPCODE_0x0_ILLEGAL(pvr) \
148 (pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK)
149 #define PVR_UNALIGNED_EXCEPTION(pvr) \
150 (pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK)
151 #define PVR_ILL_OPCODE_EXCEPTION(pvr) \
152 (pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK)
153 #define PVR_IOPB_BUS_EXCEPTION(pvr) \
154 (pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK)
155 #define PVR_DOPB_BUS_EXCEPTION(pvr) \
156 (pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK)
157 #define PVR_DIV_ZERO_EXCEPTION(pvr) \
158 (pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK)
159 #define PVR_FPU_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_FPU_EXC_MASK)
160 #define PVR_FSL_EXCEPTION(pvr) (pvr.pvr[2] & PVR2_USE_EXTEND_FSL)
162 #define PVR_DEBUG_ENABLED(pvr) (pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK)
163 #define PVR_NUMBER_OF_PC_BRK(pvr) \
164 ((pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
165 #define PVR_NUMBER_OF_RD_ADDR_BRK(pvr) \
166 ((pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
167 #define PVR_NUMBER_OF_WR_ADDR_BRK(pvr) \
168 ((pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
169 #define PVR_FSL_LINKS(pvr) ((pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7)
171 #define PVR_ICACHE_ADDR_TAG_BITS(pvr) \
172 ((pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
173 #define PVR_ICACHE_USE_FSL(pvr) (pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK)
174 #define PVR_ICACHE_ALLOW_WR(pvr) (pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK)
175 #define PVR_ICACHE_LINE_LEN(pvr) \
176 (1 << ((pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21))
177 #define PVR_ICACHE_BYTE_SIZE(pvr) \
178 (1 << ((pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
180 #define PVR_DCACHE_ADDR_TAG_BITS(pvr) \
181 ((pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
182 #define PVR_DCACHE_USE_FSL(pvr) (pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK)
183 #define PVR_DCACHE_ALLOW_WR(pvr) (pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK)
184 #define PVR_DCACHE_LINE_LEN(pvr) \
185 (1 << ((pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21))
186 #define PVR_DCACHE_BYTE_SIZE(pvr) \
187 (1 << ((pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
189 #define PVR_DCACHE_USE_WRITEBACK(pvr) \
190 ((pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14)
192 #define PVR_ICACHE_BASEADDR(pvr) (pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK)
193 #define PVR_ICACHE_HIGHADDR(pvr) (pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK)
195 #define PVR_DCACHE_BASEADDR(pvr) (pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK)
196 #define PVR_DCACHE_HIGHADDR(pvr) (pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK)
198 #define PVR_TARGET_FAMILY(pvr) ((pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24)
200 #define PVR_MSR_RESET_VALUE(pvr) \
201 (pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK)
204 #define PVR_USE_MMU(pvr) ((pvr.pvr[11] & PVR11_USE_MMU) >> 30)
205 #define PVR_MMU_ITLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_ITLB_SIZE)
206 #define PVR_MMU_DTLB_SIZE(pvr) (pvr.pvr[11] & PVR11_MMU_DTLB_SIZE)
207 #define PVR_MMU_TLB_ACCESS(pvr) (pvr.pvr[11] & PVR11_MMU_TLB_ACCESS)
208 #define PVR_MMU_ZONES(pvr) (pvr.pvr[11] & PVR11_MMU_ZONES)
212 void get_pvr(struct pvr_s *pvr);