Lines Matching refs:__u8
77 __u8 ram_addr_hi; /* shared RAM address hi byte */
78 __u8 pad0;
79 __u8 ram_addr_lo; /* shared RAM address lo byte */
80 __u8 pad1;
81 __u8 status_ctrl; /* status/control register */
82 __u8 pad2[3];
83 __u8 ram_data; /* RAM data byte at ramhi/lo */
85 __u8 pad3[23];
91 __u8 sccb_cmd; /* SCC B command reg */
92 __u8 pad4;
93 __u8 scca_cmd; /* SCC A command reg */
94 __u8 pad5;
95 __u8 sccb_data; /* SCC B data */
96 __u8 pad6;
97 __u8 scca_data; /* SCC A data */
101 __u8 wdata; /* write a data byte */
102 __u8 pad7;
103 __u8 wmark; /* write a mark byte */
104 __u8 pad8;
105 __u8 wcrc; /* write 2-byte crc to disk */
106 __u8 pad9;
107 __u8 wparams; /* write the param regs */
108 __u8 pad10;
109 __u8 wphase; /* write the phase states & dirs */
110 __u8 pad11;
111 __u8 wsetup; /* write the setup register */
112 __u8 pad12;
113 __u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */
114 __u8 pad13;
115 __u8 wones; /* mode reg: 1's set bits, 0's are x */
116 __u8 pad14;
117 __u8 rdata; /* read a data byte */
118 __u8 pad15;
119 __u8 rmark; /* read a mark byte */
120 __u8 pad16;
121 __u8 rerror; /* read the error register */
122 __u8 pad17;
123 __u8 rparams; /* read the param regs */
124 __u8 pad18;
125 __u8 rphase; /* read the phase states & dirs */
126 __u8 pad19;
127 __u8 rsetup; /* read the setup register */
128 __u8 pad20;
129 __u8 rmode; /* read the mode register */
130 __u8 pad21;
131 __u8 rhandshake; /* read the handshake register */
144 __u8 message[IOP_MSG_LEN]; /* the message being sent/received */
145 __u8 reply[IOP_MSG_LEN]; /* the reply to the message */
155 extern int iop_send_message(uint, uint, void *, uint, __u8 *,
158 extern void iop_upload_code(uint, __u8 *, uint, __u16);
159 extern void iop_download_code(uint, __u8 *, uint, __u16);
160 extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16);