Lines Matching refs:r18
297 mov r18=r0 /* make sure r18 isn't NaT */
314 shl r18=r18,16 /* compute ar.rsc to be used for "loadrs" */
323 st8 [r17]=r18,16 /* save ar.rsc value for "loadrs" */
363 .mem.offset 0,0; st8.spill [r2]=r18,16
368 mov r18=b6
400 st8 [r24]=r18,16 /* b6 */
638 adds r18=VMM_VPD_BASE_OFFSET,r21
640 ld8 r18=[r18]
642 adds r18=VMM_VPD_VIFS_OFFSET,r18
644 ld8 r18=[r18]
646 tbit.z p6,p0=r18,63
650 alloc r18=ar.pfs,0,0,0,0
961 ld8.fill r18=[r2],16
1006 // mov r18=r13
1120 ld8.fill r18=[r2],16
1178 ld8 r18=[r17] //load ar_ccv
1181 mov ar.ccv=r18
1182 shr.u r18=r20,16
1198 shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
1199 sub r19=r19,r18 // r19 = (physStackedSize + 8) - dirtySize
1248 adds r18=VMM_VPD_BASE_OFFSET,r21
1250 ld8 r18=[r18] //vpd
1254 adds r19=VMM_VPD_VPSR_OFFSET,r18
1257 mov r25=r18
1274 * r18:vpd
1280 mov r25=r18
1370 ld8 r18=[r16]
1372 adds r19=VMM_VPD_VPSR_OFFSET,r18