Lines Matching refs:VCPU
829 unsigned long vitv = VCPU(vcpu, itv);
842 if (VCPU(vcpu, itm) <= val) {
847 vcpu_set_itm(vcpu, VCPU(vcpu, itm));
854 return ((u64)VCPU(vcpu, itm));
859 unsigned long vitv = VCPU(vcpu, itv);
860 VCPU(vcpu, itm) = val;
875 VCPU(vcpu, itv) = val;
890 VCPU(vcpu, eoi) = 0;
900 vtpr.val = VCPU(vcpu, tpr);
937 ret = test_and_set_bit(vec, &VCPU(vcpu, irr[0]));
949 ret = test_and_clear_bit(vec, &VCPU(vcpu, irr[0]));
970 VCPU(vcpu, vhpi) = vhpi;
971 if (VCPU(vcpu, vac).a_int)
984 if (VCPU(vcpu, vhpi))
1087 vpsr = *(struct ia64_psr *)&VCPU(vcpu, vpsr);
1571 VCPU(vcpu, tpr) = val;
1580 VCPU(vcpu, vcr[inst.M32.cr3]) = r2;
1617 val = VCPU(vcpu, vcr[inst.M33.cr3]);
1632 old_psr = *(struct ia64_psr *)&VCPU(vcpu, vpsr);
1649 VCPU(vcpu, vpsr) = val
1657 new_psr = *(struct ia64_psr *)&VCPU(vcpu, vpsr);
1680 vpsr = *(struct ia64_psr *)&VCPU(vcpu, vpsr);
1683 VCPU(vcpu, ifs) = regs->cr_ifs;
1691 VCPU banked general register access routines
1713 unsigned long *b0 = &VCPU(vcpu, vbgr[0]);
1714 unsigned long *b1 = &VCPU(vcpu, vgr[0]);
1716 unsigned long *b0unat = &VCPU(vcpu, vbnat);
1717 unsigned long *b1unat = &VCPU(vcpu, vnat);
1720 if (VCPU(vcpu, vpsr) & IA64_PSR_BN) {
1727 VCPU(vcpu, vpsr) &= ~IA64_PSR_BN;
1749 unsigned long *b0 = &VCPU(vcpu, vbgr[0]);
1750 unsigned long *b1 = &VCPU(vcpu, vgr[0]);
1752 unsigned long *b0unat = &VCPU(vcpu, vbnat);
1753 unsigned long *b1unat = &VCPU(vcpu, vnat);
1755 if (!(VCPU(vcpu, vpsr) & IA64_PSR_BN)) {
1762 VCPU(vcpu, vpsr) |= IA64_PSR_BN;
1771 psr = VCPU(vcpu, ipsr);
1777 ifs = VCPU(vcpu, ifs);
1780 regs->cr_iip = VCPU(vcpu, iip);
1795 return (VCPU(vcpu, vpsr) & ~mask) | (regs->cr_ipsr & mask);
2049 VCPU(vcpu, vpsr) = IA64_PSR_BN;
2050 VCPU(vcpu, dcr) = 0;
2052 VCPU(vcpu, pta) = 15 << 2;
2053 VCPU(vcpu, itv) = 0x10000;
2054 VCPU(vcpu, itm) = 0;
2057 VCPU(vcpu, lid) = VCPU_LID(vcpu);
2058 VCPU(vcpu, ivr) = 0;
2059 VCPU(vcpu, tpr) = 0x10000;
2060 VCPU(vcpu, eoi) = 0;
2061 VCPU(vcpu, irr[0]) = 0;
2062 VCPU(vcpu, irr[1]) = 0;
2063 VCPU(vcpu, irr[2]) = 0;
2064 VCPU(vcpu, irr[3]) = 0;
2065 VCPU(vcpu, pmv) = 0x10000;
2066 VCPU(vcpu, cmcv) = 0x10000;
2067 VCPU(vcpu, lrr0) = 0x10000; /* default reset value? */
2068 VCPU(vcpu, lrr1) = 0x10000; /* default reset value? */