Lines Matching refs:r18
67 ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
84 ptc.e r18
86 add r18=r22,r18
89 add r18=r21,r18
100 mov r18=KERNEL_TR_PAGE_SHIFT<<2
102 ptr.i r16, r18
103 ptr.d r16, r18
113 mov r18=IA64_GRANULE_SHIFT<<2
115 ptr.i r16,r18
126 mov r18=IA64_GRANULE_SHIFT<<2
128 ptr.d r16,r18
152 ld8 r18=[r3] // Get processor state parameter on existing PALE_CHECK.
154 tbit.nz p6,p7=r18,60
160 movl r18=ia64_reload_tr;;
161 LOAD_PHYSICAL(p0,r18,ia64_reload_tr);;
162 mov b1=r18;;
168 mov r18=KERNEL_TR_PAGE_SHIFT<<2
171 mov cr.itir=r18
175 movl r18=PAGE_KERNEL
179 or r18=r17,r18
181 itr.i itr[r16]=r18
183 itr.d dtr[r16]=r18
191 ld8 r18=[r2] // load PAL PTE
202 itr.i itr[r20]=r18
212 add r18=r19,r16
219 mov cr.ifa=r18
224 mov r18 = 1
228 st8 [r2] =r18
442 // r18 processor state parameter
474 st8 [temp1]=r18 // proc_state_param
867 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
869 ptr.d r15,r18
882 mov cr.itir=r18
1042 mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps
1044 ptr.d r16,r18
1054 mov cr.itir=r18