Lines Matching refs:mov
43 mov dest=src;; \
48 mov reg=_tmp
51 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
52 mov _idx=0;; \
59 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
60 mov _idx=0;; \
67 mov _reg=rr[_tmp]
90 mov ar.lc=0x08-1;; \
95 mov rr[_idx2]=_tmp;; \
167 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
168 mov rr[_tmp1]=_tmp2
212 mov r25=pr;;
238 mov r18=KERNEL_TR_PAGE_SHIFT<<2
241 mov cr.itir=r18
242 mov cr.ifa=r17
243 mov r16=IA64_TR_KERNEL
244 mov r3=ip
265 mov cr.ipsr=r16
268 mov cr.iip=r17
269 mov cr.ifs=r0
284 mov cr.iva=r3
290 mov ar.fpsr=r2
308 (isAP) mov r2=r3
315 mov r16=-1
328 mov r17=rr[r2]
333 mov cr.itir=r17
334 mov cr.ifa=r2
336 mov r19=IA64_TR_CURRENT_STACK
346 mov IA64_KR(CURRENT)=r2 // virtual address
347 mov IA64_KR(CURRENT_STACK)=r16
348 mov r13=r2
359 mov ar.rsc=0 // place RSE in enforced lazy mode
363 mov r18=PERCPU_PAGE_SIZE
379 mov r19=r20
386 (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
387 (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
389 mov ar.bspstore=r2 // establish the new RSE stack
391 mov ar.rsc=0x3 // place RSE in eager mode
402 mov r16=num_hypervisor_hooks
411 (p7) mov b1=r9
465 mov r20=ar.lc // preserve ar.lc
466 mov ar.lc=IA64_NUM_DBG_REGS-1
467 mov r18=0
470 1: mov r16=dbr[r18]
475 mov r17=ibr[r18]
482 mov ar.lc=r20 // restore ar.lc
489 mov r20=ar.lc // preserve ar.lc
491 mov ar.lc=IA64_NUM_DBG_REGS-1
492 mov r18=-1
498 mov dbr[r18]=r16
503 mov ibr[r18]=r17
506 mov ar.lc=r20 // restore ar.lc
680 mov loc0=512
681 mov loc1=-1024+16
807 mov f32=f0 // F
812 mov f37=f0 // F
817 mov f40=f0 // F
821 mov f45=f0 // F
825 mov f48=f0 // F
829 mov f53=f0 // F
833 mov f56=f0 // F
837 mov f61=f0 // F
841 mov f64=f0 // F
845 mov f69=f0 // F
849 mov f72=f0 // F
853 mov f77=f0 // F
857 mov f80=f0 // F
861 mov f85=f0 // F
865 mov f88=f0 // F
869 * the remaining registers with simply mov instructions (F-unit).
877 mov f93=f0 // F
881 mov f96=f0 // F
885 mov f101=f0 // F
889 mov f104=f0 // F
893 mov f109=f0 // F
897 mov f112=f0 // F
901 mov f117=f0 // F
905 mov f120=f0 // F
909 mov f125=f0 // F
930 mov r15=ip
938 mov cr.ipsr=r16 // set new PSR
941 mov r19=ar.bsp
942 mov r20=sp
943 mov r14=rp // get return address into a general register
953 mov r18=ar.rnat // save ar.rnat
954 mov ar.bspstore=r17 // this steps on ar.rnat
955 mov cr.iip=r3
956 mov cr.ifs=r0
958 mov ar.rnat=r18 // restore ar.rnat
961 1: mov rp=r14
978 mov r15=ip
986 mov cr.ipsr=r16 // set new PSR
989 mov r14=rp // get return address into a general register
998 mov sp=r20
1004 mov r18=ar.rnat // save ar.rnat
1005 mov ar.bspstore=r19 // this steps on ar.rnat
1006 mov cr.iip=r3
1007 mov cr.ifs=r0
1009 mov ar.rnat=r18 // restore ar.rnat
1012 1: mov rp=r14
1020 mov r2=ar.lc
1023 mov ar.lc=r32
1031 mov ar.lc=r2
1055 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1102 mov out0 = r9
1103 mov out1 = r11;;
1105 mov out0 = r8
1119 mov reg=r32; \
1145 mov b1=r18 // Return location
1148 mov b2=r18 // doing tlb_flush work
1149 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1152 mov cr.iip=r17
1154 mov cr.ipsr=r16
1155 mov cr.ifs=r0;;
1193 mov pr=r17,-1;;