Lines Matching defs:clob0
170 .macro ____MOV_TO_KR kr, reg, clob0, clob1
171 .ifc "\clob0", "r9"
172 .error "clob0 \clob0 must not be r9"
184 .ifnc "\clob0", "r8"
185 mov \clob0 = r8
196 .ifnc "\clob0", "r8"
197 mov r8 = \clob0
201 .macro __MOV_TO_KR kr, reg, clob0, clob1
202 .ifc "\clob0", "r9"
203 ____MOV_TO_KR \kr, \reg, \clob1, \clob0
207 ____MOV_TO_KR \kr, \reg, \clob1, \clob0
211 ____MOV_TO_KR \kr, \reg, \clob0, \clob1
214 #define MOV_TO_KR(kr, reg, clob0, clob1) \
215 __MOV_TO_KR IA64_KR_ ## kr, reg, clob0, clob1
327 #define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \
328 mov clob0 = 1; \
331 st4 [clob1] = clob0 \
334 #define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \
338 movl clob0 = XSI_PSR_IC; \
340 st4 [clob0] = clob1
366 #define RSM_PSR_I(pred, clob0, clob1) \
367 movl clob0 = XSI_PSR_I_ADDR; \
370 ld8 clob0 = [clob0]; \
372 (pred) st1 [clob0] = clob1
374 #define RSM_PSR_I_IC(clob0, clob1, clob2) \
375 movl clob0 = XSI_PSR_I_ADDR; \
378 ld8 clob0 = [clob0]; \
382 st1 [clob0] = clob2; \
389 #define RSM_PSR_BE_I(clob0, clob1) \
390 RSM_PSR_I(p0, clob0, clob1); \
396 #define BSW_0(clob0, clob1, clob2) \
400 movl clob0 = XSI_BANK1_R16; \
403 .mem.offset 0, 0; st8.spill [clob0] = r16, 16; \
406 .mem.offset 0, 0; st8.spill [clob0] = r18, 16; \
409 .mem.offset 0, 0; st8.spill [clob0] = r20, 16; \
412 .mem.offset 0, 0; st8.spill [clob0] = r22, 16; \
415 .mem.offset 0, 0; st8.spill [clob0] = r24, 16; \
418 .mem.offset 0, 0; st8.spill [clob0] = r26, 16; \
421 .mem.offset 0, 0; st8.spill [clob0] = r28, 16; \
424 .mem.offset 0, 0; st8.spill [clob0] = r30, 16; \
428 movl clob0 = XSI_B1NAT; \
430 st8 [clob0] = clob1; \
432 movl clob0 = XSI_BANKNUM; \
434 st4 [clob0] = r0
477 #define BSW_1(clob0, clob1) XEN_BSW_1(clob1)